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Part: AN457
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Philips Semiconductors
Application note
80C51 External Memory Interfacing
AN457
INTRODUCTION
The '51 family is arguably the most popular 8-bit embedded controller lineup thanks to efficient yet powerful architecture, multi-sourcing by the world's top semiconductor companies and unprecedented third-party tool support. A byproduct of the chip's popularity is a lot of technical know-how embodied in legions of experienced system designers and software programmers. However, since the chips continue to attract new applications and customers, it shouldn't be taken for granted that `everyone' already knows how to design it in. Evidence to the contrary is the fact that many of the FAQs (Frequently Asked Questions) continue to be frequently asked. This application note is written to assist those designers new to the '51 family who typically fit into one or more of the following categories: Designers of extremely cost conscious systems that could previously only afford discrete logic or 4-bit solutions now upgrading their designs with superior price/performance and easier to program 8-bit microprocessors. Designers that previously used different micros and are now switching to the '51 family. New designers, most of whom were quite young at the time of the '51 introduction when design techniques were actively disseminated. In addition, even experienced designers might find it useful to review this application note, since many of the traditional design techniques and `conventional wisdom' have been superceded by faster CPUs and memories, changing timing specifications and more sophisticated application requirements. Indeed, those who have simply done it the way somebody else did it before are advised to confirm the validity of their design assumptions. The application note starts with a basic description of the '51 family memory organization and expansion bus characteristics. Since all the technical details are completely documented in the data sheet and other application notes (see the references section at the end), this section simply highlights the basic operation and timing considerations. Next, the operation and characteristics of the most often used memories specifically JEDEC standard byte-wide EPROMs and SRAMs are described. Specifications are presented for a variety of actual memories. Having described the CPU and memories, timing analysis is performed for a typical system configuration. The goal of this section is to illustrate how to answer one of the most frequently asked FAQs "What speed memory should I use with my xxMHz CPU?".
'51 FAMILY MEMORY ORGANIZATION
Though dozens of derivatives, are offered, all '51 family members share a common memory architecture and similar expansion bus. For this application note, the 80C31/8XC51 (Figure 1) will be used. The only difference between these two devices is that the 80C31 has no on-chip instruction memory while the 8XC51 has 4KB of ROM (80C51) or EPROM (87C51) instruction memory on-chip. The entire range of '51 family derivatives encompasses devices with 0KB (80C31) to 64KB (8XCE560) of on-chip instruction memory of various types including ROM, EPROM (window package), OTP (One Time Programmable), and even EEPROM. A primary characteristic is that the '51 is logically a `Harvard' machine referring to an organization consisting of separate instruction and data buses. One key byproduct is that the '51 family offers twice the memory expandability (64KB each of code and data) compared to most other 8-bit micros (typically 64KB total).
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DUAL IN-LINE PACKAGE
40 V CC 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA/VPP 30 ALE/PROG 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8
SU00098
Figure 1. 80C31/8XC51 Pinout
1996 May 15
1
Philips Semiconductors
Application note
80C51 External Memory Interfacing
AN457
As shown in Figure 2, the CPU operates in one of two modes determined at reset (RST pin) by the state of the EA (External Access) pin. If EA is asserted, on-chip instruction (but not data) memory is disabled and the entire 64KB of instruction space is accessed externally (this is the only option for the 80C31). Otherwise (EA deasserted), on-chip instruction memory is enabled and only addresses beyond the end of on-chip instruction memory (i.e., 1000H for the 8XC51) are accessible externally. The situation for on-chip data memory (i.e., RAM) is somewhat different. First, all '51 family devices include a basic complement of on-chip RAM comprised of CPU register banks, SFRs (Special Function Registers, i.e., built-in I/O functions such as UART, timer, etc.) and general purpose RAM. The on-chip data memory for the 80C31/8XC51 is shown in Figures 3 and 4. By convention, which is
used in this application note, a CPU said to have `xx' bytes of RAM (which varies from 64 bytes to 1.5 KB across the '51 family) actually contains `xx' bytes of `general purpose RAM' in addition to the space (128 bytes) allocated to SFRs. Unlike instruction memory, the state of the EA pin at reset doesn't affect on-chip data RAM which is always enabled and accessible. Another difference is related to the way the presence of on-chip RAM affects the external data memory space. For CPUs with up to 256 bytes of on-chip RAM, the full 64KB external data space is available. Devices with more than 256 bytes of RAM map the excess portion (i.e., 768 bytes for a CPU with 1K bytes of RAM) to the bottom of the external address space (Figure 5). In this case, an SFR bit (ARD Auxillary RAM Disable) determines whether the accesses to the lower space are on- or off-chip.
FFFF
FFFF
60k BYTES EXTERNAL OR 64k BYTES EXTERNAL
1000 AND 0FFF 4k BYTES INTERNAL 0000 0000
SU00567
Figure 2. Program/Data Memory Map
7FH
FFH Upper 128 80H 7FH Lower 128 0 Accessible by Direct and Indirect Addressing Accessible by Indirect Addressing Only Accessible by Direct Addressing
FFH Bank Select Bits in PSW 11 Ports, Status and Control Bits, Timer, Registers, Stack Pointer, Accumulator (Etc.) 18H 10 10H 0FH 01 08H 07H 00 Reset Value of Stack Pointer 17H 4 Banks of 8 Registers R0-R7 2FH Bit-Addressable Space (Bit Addresses 0-7F) 20H 1FH
80H
Special Function Registers
SU00463
0
Figure 3. On-chip RAM Memory Map 256 Bytes Internal Data Memory
SU00464
Figure 4. On-chip RAM Memory Map 256 Bytes Lower 128 Bytes of Internal RAM
1996 May 15
2
Philips Semiconductors
Application note
80C51 External Memory Interfacing
AN457
64 K
64 K
EXTERNAL
32768 OVERLAPPED SPACE 32767 32767 255 INTERNAL (EA = 1) EXTERNAL (EA = 0) 127 DIRECT AND INDIRECT 0 0 0 AUXILIARY RAM 0 INDIRECT ONLY SPECIAL FUNCTION REGISTERS
768 (ARD = 0) (ARD = 1)
PROGRAM MEMORY
INTERNAL DATA MEMORY
EXTERNAL DATA MEMORY
SU00695
Figure 5. On-chip RAM Memory Map > 256 Bytes
80C31/8XC51 EXPANSION BUS INTERFACE
'51 family devices with 40 or more pins generally feature four I/O ports (P0P3). P0, P2 and a portion of P3 (two pins, RD and WR), along with dedicated ALE (Address Latch Enable) and PSEN (Program Store Enable) pins, comprise the expansion bus interface.
Thus, there are three types of external access instruction read (PSEN), data read (RD) and data write (WR) as shown in Figures 6, 7, and 8. From this brief description, a number of system design implications can be drawn. ALE is essentially a continuous clock that runs at 1/6 the oscillator frequency regardless of the mix of internal and external accesses. However, note that one ALE cycle is skipped during external data access. The skipping of the ALE cycle and assertion of RD or WR only occur during external data access. The MOVX instruction, and only the MOVX instruction, performs external data access. Thus, if the program contains no MOVX instructions, ALE can be used as a timebase (i.e., no skipping) and RD and WR as general purpose outputs. External program reads (PSEN), whatever the address or cause (i.e., fetch beyond the end of internal instruction memory or EA pin asserted at reset) always use 16-bit addresses and thus require all pins of P0 and P2. [P0 & P2 can be used for general purpose I/O during non-PSEN times? P0 SFR is overwritten by PSEN but what about P2?] External data accesses affect on P0 and P2 is a little more complicated. 16-bit address accesses (MOVX using DPTR) always drive P0 and P2 with A0A15. However, 8-bit address accesses (MOVX using Ri) instead drive P2 with the value programmed into the P2 SFR, i.e., P2 is essentially general purpose I/O during an 8-bit address external data access. However, while the P0 SFR is overwritten by any external data access, the P2 SFR is only modified temporarily for the duration of a 16-bit address (DPTR) access. Subsequently, the P2 SFR is restored to whatever value it contained prior to the external data access.
P0.0P0.7
For both program and data access, P0 is used as a multiplexed address/data bus (AD07) that outputs the low order address bits (A0A7) and inputs/outputs the 8-bit data (D0D7). Note that P0 is open collector, so pull-up resistors are typically required when interfacing to external memory or I/O chips.
P2.0P2.7
For all external program accesses, P2 outputs the high order address bits (A8A15). The same is true for external data accesses with 16-bit addresses (MOVX A,@DPTR and MOVX @DPTR,A). However, external data accesses with 8-bit addresses (MOVX A,@Ri and MOVX @Ri,A) do not affect P2.
ALE (Address Latch Enable)
ALE is used to demultiplex the AD07 bus. At the beginning of the external cycle ALE is high and the CPU emits A0A7 which should be externally latched when ALE goes low. Note that ALE is always active, even during internal program and data accesses.
PSEN (Program Store Enable)
PSEN is the read strobe for external instruction access. Unlike ALE, PSEN is not asserted during internal accesses.
RD (Data Read)
RD is the read strobe for external data access and (like PSEN) is not asserted during internal accesses.
WR (Data Write)
WR is the write strobe for external data access and (like PSEN and RD) is not asserted during internal accesses.
1996 May 15
3
Philips Semiconductors
Application note
80C51 External Memory Interfacing
AN457
State 1 P1 P2
State 2 P1 P2
State 3 P2 P1
State 4 P1 P2
State 5 P1 P2
State 6 P1 P2
State 1 P1 P2
State 2 P1 P2
XTAL2:
ALE:
PSEN:
Data Sampled PCL Out
Data Sampled PCL Out
Data Sampled PCL Out
P0:
P2:
PCH Out
PCH Out
PCH Out
SU00557
Figure 6. External Program Memory Fetches
State 4 P1 P2
State 5 P1 P2
State 6 P1 P2
State 1 P1 P2
State 2 P1 P2
State 3 P1 P2
State 4 P1 P2
State 5 P1 P2
XTAL2:
ALE:
RD: PCL Out if Program Memory Is External Data Sampled DPL or RI Out Float Float
P0:
P2:
PCH or P2 SFR
DPH or P2 SFR Out
PCH or P2 SFR
SU00558
Figure 7. External Data Memory Read Cycle
1996 May 15
4
Philips Semiconductors
Application note
80C51 External Memory Interfacing
AN457
State 4 P1 P2
State 5 P1 P2
State 6 P1 P2
State 1 P1 P2
State 2 P1 P2
State 3 P1 P2
State 4 P1 P2
State 5 P1 P2
XTAL2:
ALE:
WR: PCL Out if Program Memory Is External
P0:
DPL or RI Out
Data Out
PCL Out
P2:
PCH or P2 SFR
DPH or P2 SFR Out
PCH or P2 SFR
SU00559
Figure 8. External Data Memory Write Cycle Table 1 summarizes the usage and modification of the P0 and P2 SFRs depending on the cycle type. Exploiting this information, system designers can make optimal use of all pins depending on the system configuration. For instance, systems that make no external program accesses and only 8-bit address external data accesses are free to use P2 for general purpose I/O. Just remember that CPUs with more than 256 bytes of on-chip RAM must use 16-bit addresses (DPTR) to perform external data access.
Table 1. P0 and P2 SFR Usage During External Memory Access
DURING ACCESS EXTERNAL ACCESS TYPE P0 SFR Instruction Access Data Access 8-bit Address (MOVX using Ri) Data Access 16-bit Address (MOVX using DPTR) 0FFH 0FFH 0FFH P2 SFR 0FFH Prev. Value 0FFH P0 SFR 0FFH 0FFH 0FFH P2 SFR 0FFH Prev. Value Prev. Value AFTER ACCESS
1996 May 15
5
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AN-1 AN-2 AN-3 AN-4 AN-5 AN-6 AN-7 AN-8
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