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Part: AN461
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INTEGRATED CIRCUITS
ABSTRACT This application note describes the three methods that can be used to program the Flash code memory of the 89C51Rx+/Rx2/66x families of microcontrollers. It discusses in detail the operation of the In-System Programming (ISP) capability which allows these microcontrollers to be programmed while mounted in the end product. These microcontrollers also have an In-Application Programming (IAP) capability which allows them to be programmed under firmware control of the embedded application. This capability is also described.
AN461 In-circuit and In-application programming of the 89C51Rx+/Rx2/66x microcontrollers
Author: Bill Houghton Supersedes data of 2000 Jan 05 IC20 Data Handbook 2000 Jan 13
Philips Semiconductors
Philips Semiconductors
Application note
In-circuit and In-application programming of the 89C51Rx+/Rx2/66x microcontrollers
AN461
INTRODUCTION
This document gives a brief list of features for the 89C51Rx+/Rx2/66x family of microcontrollers with Flash memory, and the ways that the Flash memory can be programmed.
The Flash Program Memory can be programmed using three different methods:
Application Note)
· The traditional parallel programming method (not described in this · A new In-System Programming method (ISP) through the serial
port
MCU FEATURES
· 80C51 CPU · 8K,16K,32K,64 KB Flash EPROM · Flash EPROM is sectored to allow the user to erase and
reprogram sectors
· In Application programming method (IAP) under control of a
running microcontroller application program
· 1 KB Masked BOOTROM for In-System Programming of the
Flash EPROM
· User callable BOOTROM subroutines for Flash erase and
programming
· Can automatically run user program or BOOTROM program at
power-up
· erase and blank check Flash memory · program and read / verify Flash memory · program and verify security bits, status byte and boot vector · read signature bytes · full-chip erase
Memory Spaces
Code memory on Philips Flash microcontrollers is organized into sectors of 8KB or 16KB, as indicated below. Different amounts of memory are present depending on the specific device as shown in Table 1 below.
Programming functions support the following functions:
· Three security bits · Fully static operation: 0 to 33Mhz @ 12 clocks/instruction; 0 to
20MHz @ 6 clocks/instruction
· 100% code and pin compatibility with 80C52 · Packages: 44-pin PLCC, 44-pin QFP, 40-pin DIP
Device 89C51RB+ 89C51RB2 89C51RC+ 89C51RC2 89C51RD+ 89C51RD2 89C660 89C662 89C664 Total Memory 16KB 16KB 32KB 32KB 64KB 64KB 16KB 32KB 64KB 8KB (01FFF) X X X X X X X X X
Table 1. Memory Block of Philips Flash Microcontrollers
8KB (20003FFF) X X X X X X X X X X X X X X X X X X X X X 16KB (40007FFF) 16KB (8000BFFF) 16KB (C000FFFF)
General Overview of In-System Programming (ISP)
In-System Programming (ISP) is a process whereby a blank device mounted to a circuit board can be programmed with the end-user code without the need to remove the device from the circuit board. Also, a previously programmed device can be erased and reprogrammed without removal from the circuit board. In order to perform ISP operations the microcontroller is powered up in a special "ISP mode". ISP mode allows the microcontroller to communicate with an external host device through the serial port, such as a PC or terminal. The microcontroller receives commands and data from the host, erases and reprograms code memory, etc. Once the ISP operations have been completed the device is reconfigured so that it will operate normally the next time it is either reset or power removed and reapplied. All of the Philips microcontrollers shown in Table 1 have a 1KB factory-masked ROM located in the upper 1KB of code memory
space from FC00 to FFFF. This 1KB ROM is in addition to the memory blocks shown in Table 1. This ROM is referred to as the "Bootrom". This Bootrom contains a set of instructions which allows the microcontroller to perform a number of Flash programming and erasing functions. The Bootrom also provides communications through the serial port. The use of the Bootrom is key to the concepts of both ISP and In-Application Programming (IAP). The contents of the bootrom are provided by Philips and masked into every device. When the device is reset or power applied, and the EA/ pin is high or at the VPP voltage, the microcontroller will start executing instructions from either the user code memory space at address 0000-h ("normal mode") or will execute instructions from the Bootrom (ISP mode). Selection of these modes will be described later.
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Philips Semiconductors
Application note
In-circuit and In-application programming of the 89C51Rx+/Rx2/66x microcontrollers
General Overview of In-Application Programming (IAP)
The Bootrom routines which perform functions on the Flash memory during ISP mode such as programming, erasing, and reading, are also available to end-user programs. Thus it is possible for an end-user application to perform operations on the Flash memory. A common entry point (FFF0h) to these routines has been provided to simplify interfacing to the end-users application. Functions are performed by setting up specific registers as required by a specific operation and performing a call to the common entry point. Like any other subroutine call, after completion of the function, control will return to the end-user's code. The Bootrom is shadowed with the user code memory in the address range from FC00h to FFFFh. This shadowing is controlled by the ENDBOOT bit (AUXR1.5). When set, accesses to internal code memory in this address range will be from the boot ROM. When cleared, accesses will be from the user's code memory. It will be NECESSARY for the end-user's code to set the ENBOOT bit prior to calling the common entry point for IAP operations, even for devices with 16KB and 32KB of internal code memory. (ISP operation is selected by certain hardware conditions and control of the ENBOOT bit is automatic when ISP mode is activated).
BOOTROM (1KB SHADOWED) BLOCK 4 (16 KB) BLOCK 3 (16 KB) BLOCK 2 (16 KB) BLOCK 1 (8 KB) BLOCK 0 (8 KB) 64KB DEVICES 32KB DEVICES 16KB DEVICES
SU01344
AN461
your application to an external circuit in order to use this feature. The VPP supply should be decoupled and VPP not allowed to exceed datasheet limits.
VCC V PP RST +12V/5V* 0.1µF VCC X1 TxD RxD +5V TxD RxD V SS X2 V SS
*Depends on specific device see text
SU01044
Figure 2. In-System Programming with a Minimum of Pins In order to understand how ISP works it is necessary to first discuss two special Flash registers; the BOOT VECTOR and the STATUS BYTE. At the falling edge of reset the MCU examines the contents of the Status Byte. If the Status Byte is set to zero, power-up execution starts at location 0000H which is the normal start address of the user's application code. When the Status Byte is set to a value other than zero, the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to 00H. The factory default setting is 0FCH, corresponds to the address 0FC00H for the factory masked-ROM ISP boot loader (Boot ROM). A custom boot loader can be written with the Boot Vector set to the custom boot loader. NOTE: When erasing the Status Byte or Boot Vector, both bytes are erased at the same time. It is necessary to reprogram the Boot Vector after erasing and updating the Status Byte. The boot loader can also be executed by holding PSEN low, EA' greater than VIH (such as +12V), and ALE HIGH (or not connected) at the falling edge of RESET. This is the same effect as having a non-zero status byte. This allows an application to be built that will normally execute the end user's code but can be manually forced into ISP operation.
Figure 1. Memory Space in Flash Microcontrollers
IN-SYSTEM PROGRAMMING (ISP)
The Philips In-System Programming (ISP) facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins: TxD, RxD, VSS, VCC, and VPP (see Figure 2). Only a small connector needs to be available to interface
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Philips Semiconductors
Application note
In-circuit and In-application programming of the 89C51Rx+/Rx2/66x microcontrollers
AN461
PROGRAM MEMORY 0000 ENBOOT = 0 Reset
2000 00
4000
Status Byte
=0 8000 Low ENBOOT = 1 C000 Boot Vector High PSEN
FC00 Boot ROM FFFF AUXR1
ENBOOT
SU01360
Figure 3. ISP Flow Chart The ISP feature allows programming of the Flash EPROM through the serial port. The ISP programming is accomplished by serial boot loader subroutines found in the BOOTROM. These routines use Intel hex records to receive commands and data from external sources such as a host PC. (Details of these hex records are described in a later section of this application note.) The Boot ROM code is located at memory address FC00H and can be invoked by selecting values for the Status Byte and the Boot Vector. After programming the Flash, the status byte should be programmed to zero in order to allow execution of the user's application code beginning at address 0000H. We recommend using the following sequence for ISP programming. Refer to Table 2 for data record structure: 1. Enter the ISP mode by applying one of the methods previously described (non-zero Status Byte, PSEN, etc.). 2. Send an uppercase "U" from the host to the microcontroller to autobaud. 3. Send a record from the host to the microcontroller to specify the oscillator frequency. 4. Send a record from the host to the microcontroller to erase the desired block(s). 5. Send records from the host to the microcontroller to program desired data into the device. 6. Erase both Status Byte and Boot Vector after ISP has been successfully done. There is no way to erase the Status Byte without erasing the Boot Vector. 7. Program the Boot Vector back to the original value (0FCH) if the you want to keep the default serial loader as the ISP communication channel. 8. Write 00H to the Status Byte so that the program will begin at address 0000H after reset.
Using the In-System Programming (ISP)
The ISP feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the 89C51Rx+/Rx2/66x to establish the baud rate. The ISP firmware provides auto-echo of received characters. Once baud rate initialization has been performed, the ISP firmware will only accept Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below: :NNAAAARRDD..DDCC
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Philips Semiconductors
Application note
In-circuit and In-application programming of the 89C51Rx+/Rx2/66x microcontrollers
In the Intel Hex record, the "NN" represents the number of data bytes in the record. The 89C51Rx+/Rx2/66x will accept up to 16 (10H) data bytes. The "AAAA" string represents the address of the first byte in the record. If there are zero bytes in the record this field is often set to 0000. The "RR" string indicates the record type. A record type of "00" is a data record. A record type of "01" indicates the end-of-file mark. In this application additional record types will be added to indicate either commands or data for the ISP facility. The maximum number of data bytes in a record is limited to 16 (decimal). ISP commands are summarized in Table 2. As a record is received by the 89C51Rx+/Rx2/66x the information in the record is stored internally and a checksum calculation is performed. The operation indicated by the record type is not performed until the entire record has been received. Should an error occur in the checksum, the 89C51Rx+/Rx2/66x will send an "X" out the serial port indicating a checksum error. If the checksum calculation is found to match the checksum in the record then the command will be executed. In most cases successful reception of the record will be indicated by transmitting a "." character out the
AN461
serial port (displaying the contents of the internal program memory is an exception). In the case of a Data Record (record type 00) an additional check is made. A "." character will NOT be sent unless the record checksum matched the calculated checksum and all of the bytes in the record were successfully programmed. For a data record an "X" indicates that the checksum failed to match and an "R" character indicates that one of the bytes did not properly program. It is necessary to send a type 02 record (specify oscillator frequency) to the 89C51Rx+/Rx2/66x before programming data. The ISP facility was designed so that specific crystal frequencies were not required in order to generate baud rates or time the programming pulses. The user thus needs to provide the 89C51Rx+/Rx2/66x with information required to generate the proper timing. Record type 02 is provided for this purpose. WinISP, a software utility to implement ISP programming with a PC, is available from the Philips website (www.semiconductors.philips.com).
Table 2. Intel-Hex Records Used by In-System Programming
RECORD TYPE 00 COMMAND/DATA FUNCTION Program Data :nnaaaa00dd....ddcc Where: Nn = number of bytes (hex) in record Aaaa = memory address of first byte in record dd....dd = data bytes cc = checksum Example: :10008000AF5F67F0602703E0322CFA92007780C3FD End of File (EOF), no operation :xxxxxx01cc Where: xxxxxx = required field, but value is a "don't care" cc = checksum Example: :00000001FF Specify Oscillator Frequency :01xxxx02ddcc Where: xxxx = required field, but value is a "don't care" dd = integer oscillator frequency rounded down to nearest MHz cc = checksum Example: :0100000210ED (dd = 10h = 16, used for 16.016.9 MHz)
01
02
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AN-1 AN-2 AN-3 AN-4 AN-5 AN-6 AN-7 AN-8
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