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Part: AN80CHW
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Phlips Semiconductors
80C51 Family
80C51 family hardware description
HARDWARE DESCRIPTION
This chapter provides a detailed description of the 80C51 microcontroller (see Figure 1). Included in this description are: 0 and 2, in bus operations
· The port drivers and how they function both as ports and, for Ports · The Timers/Counters
P0.0-P0.7
· The Serial Interface · The Interrupt System · Reset · The Reduced Power Modes in CMOS devices · The EPROM version of the 80C51
P2.0-P2.7
VCC V SS
Port 0 Drivers
Port 2 Drivers
RAM Address Register
RAM
Port 0 Latch
Port 2 Latch
EPROM/ ROM
ACC
Stack Pointer
B Register
TMP2
TMP1
Program Address Register PCON T2CON TL1 SCON TH0 TMOD TL0 TCON TH1 Buffer
ALU
SBUF
IE
IP
PC Incrementer
Interrupt, Serial Port, and Timer Blocks PSW Program Counter
PSEN ALE EA RST
Timing and Control
Instruction Register
DPTR
PD Port 1 Latch Port 3 Latch
Oscillator Port 1 Drivers XTAL1 XTAL2 Port 3 Drivers
P1.0-P1.7
P3.0-P3.7
SU00529
Figure 1. 80C51 Architecture
1996 Aug 12
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Phlips Semiconductors
80C51 Family
80C51 family hardware description
Special Function Registers
A Map of the on-chip memory area called the Special Function Register (SFR) space is shown in Figure 2. Note that in the SFRs not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have no effect. User software should not write 1s to these unimplemented locations, since they may be used in other 80C51 Family derivative products to invoke new features. The functions of the SFRs are described in the text that follows. Accumulator ACC is the Accumulator register. The mnemonics for Accumulator-Specific instructions, however, refer to the Accumulator simply as A. B Register The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register. Program Status Word The PSW register contains program status information as detailed in Figure 3. Stack Pointer The Stack Pointer register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at locations 08H. Data Pointer The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.
Ports 0 to 3 P0, P1, P2, and P3 are the SFR latches of Ports 0, 1, 2, and 3, respectively. Writing a one to a bit of a port SFR (P0, P1, P2, or P3) causes the corresponding port output pin to switch high. Writing a zero causes the port output pin to switch low. When used as an input, the external state of a port pin will be held in the port SFR (i.e., if the external state of a pin is low, the corresponding port SFR bit will contain a 0; if it is high, the bit will contain a 1). Serial Data Buffer The Serial Buffer is actually two separate registers, a transmit buffer and a receive buffer. When data is moved to SBUF, it goes to the transmit buffer and is held for serial transmission. (Moving a byte to SBUF is what initiates the transmission.) When data is moved from SBUF, it comes from the receive buffer. Timer Registers Basic to 80C51 Register pairs (TH0, TL0), and (TH1, TL1) are the 16-bit Counting registers for Timer/Counters 0 and 1, respectively. Control Register for the 80C51 Special Function Registers IP, IE, TMOD, TCON, SCON, and PCON contain control and status bits for the interrupt system, the Timer/Counters, and the serial port. They are described in later sections.
Port Structures and Operation
All four ports in the 80C51 are bidirectional. Each consists of a latch (Special Function Registers P0 through P3), an output driver, and an input buffer. The output drivers of Ports 0 and 2, and the input buffers of Port 0, are used in accesses to external memory. In this application, Port 0 outputs the low byte of the external memory address, time-multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the Port 2 pins continue to emit the P2 SFR content.
8 BYTES F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 IP P3 IE P2 SCON P1 TCON P0 TMOD SP BIT ADDRESSABLE TL0 DPL TL1 DPH TH0 TH1 PCON SBUF PSW ACC B FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87
SU00530
Figure 2. 80C51 SFR Memory Map
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Phlips Semiconductors
80C51 Family
80C51 family hardware description
MSB CY BIT PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0 AC F0 RS1 RS0 OV --
LSB P
SYMBOL CY AC F0 RS1 RS0 OV -- P
FUNCTION Carry flag. Auxilliary Carry flag. (For BCD operations.) Flag 0. (Available to the user for general purposes.) Register bank select control bit 1. Set/cleared by software to determine working register bank. (See Note.) Register bank select control bit 0. Set/cleared by software todetermine working register bank. (See Note.) Overflow flag. User-definable flag. Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the Accumulator, i.e., even parity.
NOTE: The contents of (RS1, RS0) enable the working register banks as follows: (0,0) -- Bank 0 (00H07H) (0,1) -- Bank 1 (08H0fH) (1,0) -- Bank 2 (10H17H) (1,1) -- Bank 3 (18H17H) Figure 3. Program Status Word (PSW) Register All the Port 3 pins are multifunctional. They are not only port pins, but also serve the functions of various special features as listed below: Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Function RxD (serial input port) TxD (serial output port) INT0 (external interrupt) INT1 (external interrupt) T0 (Timer/Counter 0 external input) T1 (Timer/Counter 1 external input) WR (external Data Memory write strobe) RD (external Data Memory read strobe)
SU00531A
being used as the ADDR/DATA BUS for external memory during normal operation.) To be used as an input, the port bit latch must contain a 1, which turns off the output driver FET. Then, for Ports 1, 2, and 3, the pin is pulled high by a weak internal pullup, and can be pulled low by an external source. Port 0 differs in that its internal pullups are not active during normal port operation. The pullup FET in the P0 output driver (see Figure 4) is used only when the port is emitting 1s during external memory accesses. Otherwise the pullup FET is off. Consequently P0 lines that are being used as output port lines are open drain. Writing a 1 to the bit latch leaves both output FETs off, so the pin floats. In that condition it can be used as a high-impedance input. Because Ports 1, 2, and 3 have fixed internal pullups, they are sometimes called "quasi- bidirectional" ports. When configured as inputs they pull high and will source current (IIL, in the data sheets) when externally pulled low. Port 0, on the other hand, is considered "true" bidirectional, because when configured as an input it floats. All the port latches in the 80C51 have 1s written to them by the reset function. If a 0 is subsequently written to a port latch, it can be reconfigured as an input by writing a 1 to it. Writing to a Port In the execution of an instruction that changes the value in a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are in fact sampled by their output buffers only during Phase 1 of an clock period. (During Phase 2 the output buffer holds the value it saw during the previous Phase 1). Consequently, the new value in the port latch won't actually appear at the output pin until the next Phase 1, which will be at S1P1 of the next machine cycle. If the change requires a 0-to-1 transition in Port 1, 2, or 3, an additional pullup is turned on during S1P1 and S1P2 of the cycle in which the transition occurs. This is done to increase the transition speed. The extra pullup can source about 100 times the current that the normal pullup can. It should be noted that the internal pullups are field-effect transistors, not linear resistors. The pullup arrangements are shown in Figure 5. 3
The alternate functions can only be activated if the corresponding bit latch in the port SFR contains a 1. Otherwise the port pin remains at 0. I/O Configurations Figure 4 shows a functional diagram of a typical bit latch and I/O buffer in each of the four ports. The bit latch (one bit in the port's SFR) is represented as a Type D flip-flop, which will clock in a value from the internal bus in response to a "write to latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read pin" signal from the CPU. Some instructions that read a port activate the "read latch" signal, and others activate the "read pin" signal. As shown in Figure 4, the output drivers of Port 0 and 2 are switchable to an internal ADDR and ADDR/DATA bus by an internal CONTROL signal for use in external memory accesses. During external memory accesses, the P2 SFR remains unchanged, but the P0 SFR gets 1s written to it. Also shown in Figure 4 is that if a P3 bit latch contains a 1, then the output level is controlled by the signal labeled "alternate output function." The actual P3.X pin level is always available to the pin's alternate input function, if any. Ports 1, 2, and 3 have internal pullups, and Port 0 has open drain outputs. Each I/O line can be independently used as an input or an output. (Port 0 and 2 may not be used as general purpose I/O when
1996 Aug 12
Phlips Semiconductors
80C51 Family
80C51 family hardware description
ADDR/Data Read Latch Control
V CC Read Latch V CC Internal Pullup* P1.X Pin
P0.X Pin Int. Bus Write to Latch D P0.X Latch CL Q MUX Q Int. Bus Write to Latch D P1.X Latch CL Q Q
Read Pin
Read Pin
a. Port 0 Bit
b. Port 1 Bit
Alternate Output Function
ADDR/Data Read Latch Control V CC Internal Pullup* Read Latch
V CC Internal Pullup* P3.X Pin
MUX Int. Bus Write to Latch D P2.X Latch CL Q Q P2.X Pin Int. Bus Write to Latch D P3.X Latch CL Q Q
Read Pin
Read Pin
Alternate Input Function
c. Port 2 Bit
d. Port 3 Bit
SU00532
*See Figure 5 for details of the internal pullup. Figure 4. 80C51 Port Bit Latches and I/O Buffers In the NMOS 8051 part, the fixed part of the pullup is a depletion mode transistor with the gate wired to the source. This transistor will allow the pin to source about 0.25mA when shorted to ground. In parallel with the fixed pullup is an enhancement mode transistor, which is activated during S1 whenever the port bit does a 0-to-1 transition. During this interval, if the port pin is shorted to ground, this extra transistor will allow the pin to source an additional 30mA. In the CMOS 80C51, the pullup consists of three pFETs. It should be noted that an n-channel FET (nFET) is turned on when a logical 1 is applied to its gate, and is turned off when a logical 0 is applied to its gate. A p-channel FET (pFET) is the opposite: it is on when its gate sees a 0, and off when its gate sees a 1. pFET1 in Figure 5 is the transistor that is turned on for 2 oscillator periods after a 0-to-1 transition in the port latch. While it's on, it turns on pFET3 (a weak pullup), through the inverter. This inverter and pFET3 form a latch which holds the 1. Note that if the pin is emitting a 1, a negative glitch on the pin from some external source can turn off pFET3, causing the pin to go into a float state. pFET2 is a very weak pullup which is on whenever the nFET is off, in traditional CMOS style. It's only about 1/10 the strength of pFET1. Its function is to restore a 1 to the pin in the event the pin had a 1 and lost it to a glitch. Port Loading and Interfacing The output buffers of Ports 1, 2, and 3 can each drive 4 LS TTL inputs. These ports on NMOS versions can be driven in a normal manner by a TTL or NMOS circuit. Both NMOS and CMOS pins can be driven by open-collector and open-drain outputs, but note that 0-to-1 transitions will not be fast. In the NMOS device, if the pin is driven by an open-collector output, a 0-to-1 transition will have to be driven by the relatively weak depletion mode FET in Figure 5a. In the CMOS device, an input 0 turns off pullup pFET3, leaving only the very weak pullup pFET2 to drive the transition. Port 0 output buffers can each drive 8 LS TTL inputs. They do, however, require external pullups to drive NMOS inputs, except when being used as the ADDRESS/DATA bus for external memory.
1996 Aug 12
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Phlips Semiconductors
80C51 Family
80C51 family hardware description
2 Osc. Periods
V CC Enhancement Mode FET Depletion Mode FET
Port Pin
Q From Port Latch VS S
a. NMOS Configuration. The enhancement mode transistor is turned on for 2 oscillator periods after Q makes a 0-to-1 transition.
V CC 2 Osc. Periods
V CC
V CC
P1
P2
P3
Port Pin n
Q From Port Latch Input Data
Read Port Pin
b. CMOS Configuration. pFET1 is turned on for 2 oscillator periods after Q makes a 0-to-1 transition. During this time, pFET1 also turns on pFET3 through the inverter to form a latch which holds the 1. pFET2 is also on.
SU00533
Figure 5. Ports 1 and 3 NMOS and CMOS Internal Pullup Configurations (Port 2 is similar except that it holds the strong pullup on while emitting 1s that are address bits. See Accessing External Memory.) Read-Modify-Write Feature Some instructions that read a port read the latch and others read the pin. Which ones do which? The instructions that read the latch rather than the pin are the ones that read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write" instructions. The instructions listed below are read-modify-write instructions. When the destination operand is a port, or a port bit, these instructions read the latch rather than the pin: ANL ORL XRL JBC CPL INC DEC DJNZ (logical AND, e.g., ANL P1,A) (logical OR, e.g., ORL P2,A) (logical EX-OR, e.g., XRL P3,A) (jump if bit = 1 and clear bit, e.g., JBC P1.1,LABEL) (complement bit, e.g., CPL P3.0) (increment, e.g., INC P2) (decrement, e.g., DEC P2) (decrement and jump if not zero, e.g., DJNZ P3,LABEL) MOV PX.Y,C (move carry bit to bit Y of Port X) CLR PX.Y (clear bit Y of Port X) SET PX.Y (set bit Y of Port X) It is not obvious that the last three instructions in this list are read-modify-write instructions, but they are. They read the port byte, all 8 bits, modify the addressed bit, then write the new byte back to the latch. The reason that read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a 1 is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor and interpret it as a 0. Reading the latch rather than the pin will return the correct value of 1.
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