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Part: CDP1802ACE
Category:
Description: Ic-8-bit CMOS Cpu
Company:
Datasheet: Download CDP1802ACE datasheet File size : 31 kB
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SEMICONDUCTOR
CDP1802A, CDP1802AC, CDP1802BC
CMOS 8-Bit Microprocessors
Description
The CDP1802 family of CMOS microprocessors are 8-bit register oriented central processing units (CPUs) designed for use as general purpose computing or control elements in a wide range of stored program systems or products. The CDP1802 types include all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories. Extensive input/output (I/O) control features are also provided to facilitate system design. The 1800 series architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum flexibility and minimum cost can be realized. The 1800 series CPU also provides a synchronous interface to memories and external controllers for I/O devices, and minimizes the cost of interface controllers. Further, the I/O interface is capable of supporting devices operating in polled, interrupt driven, or direct memory access modes. The CDP1802A and CDP1802AC have a maximum input clock frequency of 3.2MHz at VDD = 5V. The CDP1802A and CDP1802AC are functionally identical. They differ in that the CDP1802A has a recommended operating voltage range of 4V to 10.5V, and the CDP1802AC a recommended operating voltage range of 4V to 6.5V. The CDP1802BC is a higher speed version of the CDP1802AC, having a maximum input clock frequency of 5.0MHz at VDD = 5V, and a recommended operating voltage range of 4V to 6.5V.
March 1997
Features
· Maximum Input Clock Maximum Frequency Options At VDD = 5V - CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . 3.2MHz - CDP1802BC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0MHz · Maximum Input Clock Maximum Frequency Options At VDD = 10V - CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . 6.4MHz · Minimum Instruction Fetch-Execute Times At VDD = 5V - CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0µs - CDP1802BC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2µs · Any Combination of Standard RAM and ROM Up to 65,536 Bytes · 8-Bit Parallel Organization With Bidirectional Data Bus and Multiplexed Address Bus · 16 x 16 Matrix of Registers for Use as Multiple Program Counters, Data Pointers, or Data Registers · On-Chip DMA, Interrupt, and Flag Inputs · Programmable Single-Bit Output Port · 91 Easy-to-Use Instructions
Ordering Information
PART NUMBER 5V - 3.2MHz CDP1802ACE CDP1802ACEX CDP1802ACQ CDP1802ACD CDP1802ACDX 5V - 5MHz CDP1802BCE CDP1802BCEX CDP1802BCQ CDP1802BCDX -40oC to +85oC -40oC to +85oC TEMPERATURE RANGE -40o C to +85 C
o
PACKAGE PDIP Burn-In PLCC SBDIP Burn-In
PKG. NO. E40.6 E40.6 N44.65 D40.6 D40.6
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© Harris Corporation 1997
File Number
1305.2
3-3
CDP1802A, CDP1802AC, CDP1802BC Pinouts
40 LEAD PDIP (PACKAGE SUFFIX E) 40 LEAD SBDIP (PACKAGE SUFFIX D) TOP VIEW 44 LEAD PLCC (PACKAGE TYPE Q) TOP VIEW
CLOCK WAIT CLEAR Q SC1 SC0 MRD BUS 7 BUS 6
1 2 3 4 5 6 7 8 9
40 VDD 38 DMA IN WAIT SC1 37 DMA OUT 36 INTERRUPT 35 MWR 34 TPA 33 TPB 32 MA7 31 MA6 30 MA5 29 MA4 28 MA3 27 MA2 26 MA1 25 MA0 24 EF1 23 EF2 22 EF3 21 EF4 SC0 MRD BUS 7 BUS 6 BUS 5 NC BUS 4 BUS 3 BUS 2 BUS 1 BUS 0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS NC EF4 EF3 EF2 EF1 MA0 VCC N2 N1 N0 39 38 37 36 35 34 33 32 31 30 29 MWR TPA TPB MA7 MA6 NC MA5 MA4 MA3 MA2 MA1 CLEAR INTERRUPT MA0-4 39 XTAL CLOCK DMA-OUT MRD CDP1824 32 BYTE RAM MWR TPA DATA CEO CS DMA-IN
6
5
4
3
2
1 44 43 42 41 40
BUS 5 10 BUS 4 11 BUS 3 12 BUS 2 13 BUS 1 14 BUS 0 15 VCC 16 N2 17 N1 18 N0 19 VSS 20
ADDRESS BUS
CDP1852 INPUT PORT
CS2 CS1
N0 MA0-7
MA0-7
MRD CDP1802 8-BIT CPU MWR DATA CS1 N1 TPA
MRD CDP1833 1K-ROM
CDP1852 CS2 OUTPUT PORT CLOCK
TPB DATA
FIGURE 1. TYPICAL CDP1802 SMALL MICROPROCESSOR SYSTEM
3-4
VDD
NC
XTAL
Q
CDP1802A, CDP1802AC, CDP1802BC Block Diagram
I/O REQUESTS MEMORY ADDRESS LINES I/O FLAGS DMA OUT DMA IN INT CONTROL CLEAR WAIT
MA7 MA5 MA3 MA1 MUX
MA6 MA4 MA2 MA0 EF1 EF3 EF2 EF4
CLOCK LOGIC
CLOCK XTAL SCO SCI Q LOGIC TPA TPB MWR MRD
STATE CODES
CONTROL AND TIMING LOGIC
SYSTEM TIMING
TO INSTRUCTION DECODE A REGISTER R(0).1 R(0).0 ARRAY R(1).1 R(1).0 R R(2).1 R(2).0 R(9).1 R(9).0 R(A).1 R(A).0 R(E).1 R(E).0 R(F).1 R(F).0 8-BIT BIDIRECTIONAL DATA BUS LATCH AND DECODE
B ALU DF INCR/ DECR
N0 X T P I N N1 N2 BUS 0 BUS 1 BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 BUS 7 I/O COMMANDS
D
FIGURE 2.
3-5
CDP1802A, CDP1802AC, CDP1802BC
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1802A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1802AC, CDP1802BC . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Information
Thermal Resistance (Typical, Note 4) JA (oC/W) JC (oC/W) PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . 50 N/A PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . 46 N/A SBDIP . . . . . . . . . . . . . . . . . . . . . . . . . 55 15 Device Dissipation Per Output Transistor TA = Full Package Temperature Range . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Package Type E and Q . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC Lead Tips Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions TA = -40oC to +85oC. For maximum reliability, operating conditions should be selected so
that operation is always within the following ranges: TEST CONDITIONS (NOTE 2) VCC (V) 4 to 6.5 4 to 10.5 Minimum Instruction Time (Note 3) 5 5 10 Maximum DMA Transfer Rate 5 5 10 Maximum Clock Input Frequency, fCL, Load Capacitance (CL) = 50pF 5 5 10 NOTES: 1. Printed circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent. 2. VCC must never exceed VDD. 3. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3 machine cycles - one Fetch and two Execute operations. 4. JA is measured with component mounted on an evaluation board in free air. CDP1802A CDP1802AC CDP1802BC
PARAMETER DC Operating Voltage Range Input Voltage Range Maximum Clock Input Rise or Fall Time
VDD (V) 4 to 6.5 4 to 10.5 5 10 10 5 10 10 5 10 10
MIN 4 VSS 5 4 2.5 DC DC DC
MAX 10.5 VDD 1 400 500 800 3.2 4 6.4
MIN 4 VSS 5 DC -
MAX 6.5 VDD 1 400 3.2 -
MIN 4 VSS 3.2 DC -
MAX 6.5 VDD 1 667 5 -
UNITS V V µs µs µs µs µs KBytes/s
MHz MHz MHz
3-6
CDP1802A, CDP1802AC, CDP1802BC
Static Electrical Specifications at TA = -40oC to +85oC, Except as Noted
TEST CONDITIONS VCC, VDD (V) 5 10 CDP1802A CDP1802AC, CDP1802BC
PARAMETER Quiescent Device Current
SYMBOL IDD
VOUT (V) -
VIN (V) -
MIN -
(NOTE 1) TYP 0.1 1
MAX 50 200
MIN -
(NOTE 1) TYP 1 -
MAX 200 -
UNITS µA µA
Output Low Drive (Sink) Current (Except XTAL) XTAL Output High Drive (Source) Current (Except XTAL) XTAL Output Voltage Low Level Output Voltage High Level Input Low Voltage VOH VIL VOL IOH 4.6 9.5 4.6 0.5, 4.5 0.5, 4.5 1, 9 Input High Voltage VIH 0.5, 4.5 0.5, 4.5 1, 9 CLEAR Input Voltage Schmitt Hysteresis VH Input Leakage Current IIN Any Input 0, 5 0, 10 0, 5 0, 10 0 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 Three-State Output Leakage Current Operating Current CDP1802A, AC at f = 3.2MHz CDP1802BC at f = 5.0MHz Minimum Data Retention Voltage Data Retention Current VDR IDR IDDI (Note 2) 5 2 4 2 4 mA IOUT 0, 5 0, 10 5 10 5 5 10 5 10 5 5, 10 10 5 5, 10 10 5 5, 10 10 5 10 5 10 -0.27 -0.55 -125 4.9 9.9 3.5 4 7 0.4 0.3 1.5 -0.55 -1.1 -250 0 0 5 10 0.5 0.4 2 ±10-4 ±10-4 ±10-4 ±10-4 0.1 0.1 1.5 1 3 ±1 ±1 ±1 ±1 -0.27 -125 4.9 3.5 0.4 -0.55 -250 0 5 0.5 ±10-4 ±10-4 0.1 1.5 ±1 ±1 mA mA µA V V V V V V V V V V V V V µA µA µA µA IOL 0.4 0.5 0.4 0, 5 0, 10 5 5 10 5 1.1 2.2 170 2.2 4.4 350 1.1 170 2.2 350 mA mA µA
-
-
5
-
-
-
-
3
6
mA
VDD = VDR VDD = 2.4V
-
2
2.4
-
2
2.4
V µA
-
0.05
-
-
0.5
-
3-7
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