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Part: CXA1854
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Datasheet: Download CXA1854 datasheet File size : 147 kB
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CXA1854AR
Decoder/Driver/Timing Generator for Color LCD Panels
Description The CXA1854AR is an IC designed exclusively to drive color LCD panels LCX009AK/AKB/LCX005BK/ BKB. This IC greatly reduces the number of circuits and parts required to drive LCD panels by incorporating RGB decoder functions for video signals, driver functions, and a timing generator for driving panels onto a single chip. Features · Color LCD panels LCX009AK/AKB/LCX005BK/BKB driver · Both NTSC/PAL compatible · Supports composite inputs, Y/C inputs and Y/color difference inputs · Band-pass filter, trap and delay line · Sharpness function · 2-point compensation circuits · R, B output delay time adjustment circuit (supports both right and left inversion) · Polarity reversed circuit / line inverted mode · Supports external RGB input · Supports line inversion · Supports AC drive for LCD panel during no signal Applications · Color LCD viewfinders · Liquid crystal projectors · Industrial monitors Structure Bipolar CMOS IC 64 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C) · Supply voltage VCC1 GND 6 · Supply voltage VCC2 GND 14 · Supply voltage VDD VSS 6 · Analog input pin voltage VINA 0.3 to VCC1
V V V V
· Digital input pin voltage VIND 0.3 to VDD + 0.3 V · Operating temperature range Topr 15 to +70 °C · Storage temperature range Tstg 40 to +150 °C · Allowable power dissipation PD (Ta 70°C) 400 mW Operating conditions · Supply voltage VCC1 GND · Supply voltage VCC2 GND · Supply voltage LCX009 mode VDD VSS LCX005 mode VDD VSS
4.6 to 5.3 11.0 to 13.0 4.5 to 5.5 2.7 to 5.5
V V V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E95X01A73
CXA1854AR
Block Diagram
BLKLIM
G OUT
R OUT
B OUT
TEST8
FB G
TEST7
V CC 1
TEST6
V CC 2
FB R
FB B
GND2
REG
RGT
48 REG. REGV B-YIN 49
47 +5V
46
45 +12V
44
43
42
41
40
39
38 GND2
37
36
35
34
33 +5V
1 VCC2 2
buf
buf
buf V-SYNC SEP 32 TEST5
R-YIN 50
CLAMP
INT/EXT PAL ID
VDD
V-POS RESET GEN DEMOD POL SW V-CTL COUNTER V-POS COUNTER
31 VD
COUT 51
PAL SW RESET XCLR
30 HD EQP BGP CLP BLK 29 HCK1
HUE/RST 52
LPF COLOR 53 APC MATRIX ACC DET R-BRT 55 COLOR CONT GAMMA KILLER RGB BRIGHT SUB CONTRAST S/H FILT CAL EXT SW CONTRAST RGB GAIN SUB BRIGHT
V-CTL DECODER
H-CTL DECODER DECODER PLL COUNTER
28 HCK2 AUX-V COUNTER H-POS COUNTER DECODER & H-TIMING PULSE GEN
XVXO 54
VXO
HUE
PS
27 HST1
26 TEST4
B-BRT 56
RGB-GAIN 57
FRP SH1 SH2 SH3 SH4
FIELD & LINE CTL PAL PULSE ELIM & MODE SEL
25 CLR
24 EN
GAMMA2 58
23 VCK1
GAMMA1 59 BPF BRIGHT 60 AGG DET CONTRAST 61 ACC AMP CIN 62
PIC CONT HALF-H KILLER AGC DL 2 H-SYNC DET H-SKEW DET MASTER SUB CK CK TEST S/R 1/7
YC/YRB/COMP SPAL/DPAL/NTSC
22 VCK2 PULSE GEN V-TIMING
21 VST1
20 TEST3
19 SLCK
R-GAIN 63
TRAP
DL 1
18 TEST0 PLL PHASE COMP
B-GAIN 64
SYNC SEP
17 TEST1
H. FILTER
CLAMP GND1
MODE SELECT
VSS 7 8 9 10 11 12 13 14 15 16
1
2
3
4
5
6
SYNCIN
GND1
EXT-B
RPD
AGCTC
AGCADJ
MODE2
MODE1
2
TEST2
PICT
EXT-G
EXT-R
CKO
YIN
VSS
CKI
CXA1854AR
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol SYNC IN Y IN AGCADJ AGCTC PICT GND1 MODE1 MODE2 EXT-R EXT-G EXT-B RPD VSS CKI CKO TEST2 TEST1 TEST0 SLCK TEST3 VST1 VCK2 VCK1 EN CLR TEST4 HST1 HCK2 HCK1 HD VD TEST5 I O I I I I O O O O O O O O O O O O I I I I I I O I/O I I I O I Sync input Y signal input AGC level adjustment AGC time constant
(H: Pull up, M: Intermediate setting, L: Pull down) Description Input pin for open status
Y signal frequency characteristics adjustment Analog 5V GND Switches between NTSC (H), DPAL (M) and SPAL (L) Switches between composite (H), Y/color difference (M) and YC input (L) External digital input R (input conditions noted separately) External digital input G (input conditions noted separately) External digital input B (input conditions noted separately) Phase comparator output Digital GND Oscillation cell input Oscillation cell output Test Test Test Switches between LCX005BK (H) and LCX009AK (L) Leave this pin open. V start pulse 1 output V clock pulse 2 output V clock pulse 1 output EN pulse output CLR pulse output Leave this pin open. H start pulse 1 output H clock pulse 2 output H clock pulse 1 output HD pulse output VD pulse output Leave this pin open. L L L L L M M
DPAL supports demodulation methods which use an external delay line during demodulation; SPAL supports methods which internally process chroma demodulation.
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CXA1854AR
Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol VDD RGT TEST6 TEST7 TEST8 GND2 R OUT FB R G OUT FB G B OUT FB B VCC2 BLKLIM VCC1 REG B-YIN R-YIN COUT HUE/RST COLOR XVXO R-BRT B-BRT RGB-GAIN GAMMA2 GAMMA1 BRIGHT CONTRAST CIN R-GAIN B-GAIN
I/O Digital 5V power supply I I I I
Description
Input pin for open status
Switches between Normal scan (H) and Reverse scan (L) Leave this pin open. Leave this pin open. Leave this pin open. Analog 12V GND
H H H H
O I O I O I
R output R signal DC voltage feedback input G output G signal DC voltage feedback input B output B signal DC voltage feedback input Analog 12V power supply
I
Black peak limiter level adjustment Analog 5V power supply
O I I O I I I I I I I I I I I I I
Constant voltage capacitor connection B-Y demodulator input (or B-Y/color difference signal input) R-Y demodulator input (or R-Y/color difference signal input) Chroma signal output (for PAL 1HDL) Hue adjustment/system reset Color adjustment VXO crystal oscillator connection R brightness adjustment B brightness adjustment RGB gain adjustment 2 adjustment 1 adjustment Brightness adjustment Contrast adjustment Chroma signal input R gain adjustment B gain adjustment
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CXA1854AR
Analog Block Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description
VCC1
200
1
SYNC IN
1 50p
Sync input. Normally inputs the Y signal. The standard signal input level is 0.5Vp-p (up to 100% white level from the sync chip).
GND1
VCC1
2
YIN
3.2V
2 1k
Y signal input. The standard signal input level is 0.5Vp-p (up to 100% white level from the sync chip). Input at low impedance (75 or less).
50µA
GND1
VCC1
40k
3
AGCADJ
VCC1/2
3 2k 2.5V GND1
AGC gain adjustment pin.
VCC1 50µA 1k
4
AGCTC
4 20k
AGC detection filter connection.
GND1
VCC1 1k 47k
5
PICT
VCC1/2
5 50µA GND1 2.5V
Adjusts frequency characteristics of luminance signal. Increasing the voltage emphasizes contours.
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