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Details, datasheet, quote on part number:ESDA6V1FU3
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Datasheet text preview:
®
ESDA6V1FUx
ESD PROTECTION MONOLITHIC 9-BIT WIDE TRANSILTM ARRAY
Application Specific Discretes A.S.D.T M
MAIN APPLICATIONS
Where protection in ESD sensitive equipment is required, such as : - Computers - Printers - Communication systems DESCRIPTION The ESDA6V1FUx is a monolithic TRANSIL array designed to provide a 9-bit wide undershoot and overshoot clamping function in association with ESD protection level of up to 25 kV. The ESDA6V1FUx provides best efficiency when using separated inputs and outputs , in the so called 4-point structure. FEATURES 9-bit wide undersho ot and overshoot clamping functions. Breakdown voltage : VBR = 6.1V min. Forward voltage VF = 1.25V max. @ IF=200mA Low capacitan ce : C =130pF @ VR M=5.25V. Low clamping voltage. 200W peak pulse power (8/20µs). BENEFITS ESD protection of 25 kV, according to MIL STD- Method 3015-6. High integration. Four points structure, avoiding all ESD effects at the outputs. COMPLIES WITH THE FOLLOWING STANDARDS : - ESD standard : . IEC 1000-4-2 Level4 SSOP20 SO20
PIN-OUT CONFIGURATION
I1 I2 I3 I4 I5 GND I6 I7 I8 I9
O1 O2 O3 O4 O5 GND O6 O7 O8 O9
15kV (air discharge) 8kV (contact discharge) - MIL STD 883C - Method 3015-6 C = 100 pF R = 1500 VP = 25 kV 3 positive strikes and 3 negative strikes (F = 1 Hz) - Human body test : C = 150 pF R = 150 VP = 4 kV
TRANSIL is a trademark of STMicroelectronics
N ovember 1998 - Ed: 1
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ESDA6V1FUx
ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol VPP Parameter Maximum electrostatic discharge in following measurement conditions: MIL STD 883C - METHOD 3015-6 I EC1000-4-2 - air discharge I EC1000-4-2 - contact discharge Peak p ulse power (8/20µs) Storage temperature Maximum junction temperature Value Unit
25 16 9 200 - 55 to + 150 125
kV
PPP T stg Tj
W °C °C
Symbol VRM VBR VCL VF C Rd IRM IPP
Parameter Stand-of f voltage Breakdown voltage Clamping voltage Forward voltage drop Capacitance Dynamic impedance Leakage current Peak p ulse current
Symbol IRM VBR VF Rd C
Test conditions VR M = 5.25 V, between any I/O pin and GND IR = 1 mA, between any I/O pin and GND IF = 200 mA, between any I/O pin and GND IP P = 15 A, tp = 2.5µs (note 1) Between any I/O pin and GND at 0 V bias Between any I/O pin and GND at VRM = 5.25 V
Min.
Typ.
Max. 20
Unit µA V V pF
6.1
7.2 1.25 0.2 260 130
Note 1 : see the calculation of the clamping v oltage.
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ESDA6V1FUx
CALCULATION OF THE CLAMPING VOLTAGE USE OF T HE DYNAMIC RESISTANCE The ESDA family has been designed to clamp f ast spikes like ESD. Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the classical parameters. The voltage across t he protection cell can be calculated with the following formula: VCL = VBR + Rd IPP Where Ipp is the peak current through the ESDA cell. DYNAMIC RESISTANCE MEASUREMENT The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the classical 8/20µs and 10/100 0µs surges. As the value of the dynamic resistance remains stable f or a surge duration lower than 20µs, the 2.5µs rectangula r surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomeno n during the measurement of Rd.
I Ipp
2µs tp = 2.5µs
t
2.5µs duration measurement wave.
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ESDA6V1FUx
Fig 1: Peak power dissipation versus initial junction temperature. Fig 2: Peak pulse power versus exponential pulse duration (Tj initial=25°C).
Ppp(W)
Ppp[Tj initial]/Ppp[Tj initial=25°C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
2000 1000
100
Tj initial(°C) 0 25 50 75 100 125 150
tp(µs) 10 1 10 100
Fig 3: Clamping voltage versus p eak pulse current (Tj initial=25°C, rectangular waveform tp=2.5µs).
Fig 4: Capacitance versus reverse applied voltage (typical values).
Ipp(A) 30.0 10.0 200
tp=2.5µs
C(pF)
F=1MHz Vosc=30mV
180 160
1.0
140 120 Vcl(V) (output voltage) VR(V) 12 100 1 2 5 10
0.1
4
5
6
7
8
9
10
11
Fig 5: Relative variation of leakage current versus junction temperature (typical values).
Fig 6: Peak forward voltage drop versus peak forward current (typical values). Rectangu lar waveform: t p = 2.5µs
IFM(A) 5.00
IR[Tj] / IR[Tj=25°C] 3.0 2.5
1.00
2.0 1.5 1.0 0.5 0.0 25 50 Tj(°C) 75 100 125
0.10
VFM(V) 0.01 0.6 0.8 1.0 1.2 1.4 1.6 1.8
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ESD protection by the ESDA6V1FUx Electrostatic discharge (ESD) is a major cause of failure in electronic systems. Transient Voltage Suppressors (TVS) are an ideal choice for ESD protection. They are capable of clamping the incoming transient to a low enough level such t hat damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice for minimal lead inductance. They serve as parallel protection elements, connected between the signal line to ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the transient current to ground. Fig. 7 : Example of connection for one cell of t he ESDA6V1FUx
The ESDA6V1FUx array is the ideal board level protection of ESD sensitive semiconductor components. It provides best efficiency when using separated inputs and outputs , in t he so called 4-points structure. Circuit Board Layout Circuit board layout is a critical design step in t he suppression of ESD induced t ransients. The following guidelines are recommended : The ESDA6V1FUx should be placed as near as possible to the input terminals or connectors. The path length between the ESD suppressor and the protected line should be minimized. All conductive loops, including power and ground loops should be minimized. The ESD transient return path to ground should be kept as short as possible. Ground planes should be used whenever possible. Fig. 8 : Recommended PCB layout to benefit from 4 point structure
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