|
Details, datasheet, quote on part number:HD64180SH-10
| |
Datasheet text preview:
HD64180SH-10 (1/3) IL11D
C-MOS 8-BIT MICROPROCESSOR
--TOP VIEW-- 60 5 55 40 45 1
DD
61
V
GND V
G
3 40
75 GND 35
70 GDD GND ND 85 25 ND 0 V
DD
20
1
5 1
10
25
PIN N I/O o. 2 1 3 4 5 6 7 8 9 1 10 11 12 13 14 15 6 I I I I I I -- O O O O O O O O
1
SIGNAL WAIT N I MI INT0 INT1 R NT2 B ESET UV REQ S B DD USACK LT R IR H EF R LT A WD MR E
PIN N I/O o. 17 18 29 20 21 22 23 24 25 26 27 28 39 30 31 2 O O O O O O -- O O O O -- O O O
SIGNAL IA E O A0 A1 A2 A3 A4 G5 AD N A6 A7 A8 G9 AND A10 A11 12
PIN N I/O o. 33 34 35 36 37 38 49 40 41 42 43 44 45 46 47 8 O -- O O O O O -- I I/O I/O I/O I/O I/O I/O /O
0
SIGNAL A13 G 14 AND A15 A16 A17 A18 V19 DD D D0 D1 D2 D3 D4 D5 6
PIN N I/O o. 5 49 50 51 52 53 54 55 56 57 58 69 60 61 62 63 4 I/O O /O I I I I I/O O /O O I -- I I I I/O /O
SIGNAL S D7 RYNC D TSM CCDM R TSM RXDM T XCM TXCM RXDM D TSA G DA C C ND R TSA RXDA T XCA XCA
PIN N I/O o. 65 66 67 68 79 70 71 72 73 74 75 76 77 78 89 0 O I I O O O -- I I -- I I O O O O
SIGNAL D XDA T DREQ0 TREQ1 TEND0 END1 o V X DD E TAL G TAL X T ND TIN0 T IN1 TOUT0 OUT1 C CS0 S1
HD64180SH-10 (2/3)
42 43 44 45 46 47 48 29 18 29 20 21 22 23 25 26 27 38 30 31 32 33 34 36 37 38 49 10
INPUT B
; BUS REQUEST CLEAR TO SEND FOR ASCI/CSIO CLEAR TO SEND FOR MSCI DATA CARRIER DETECT FOR ASCI/CSIO DATA CARRIER DETECT FOR MSCI DMA REQUEST FOR CHANNEL EXTERNAL CLOCK INPUT/CRYSTAL CONNECTION INTERRUPT 0, 1, 2 NON-MASKABLE INTERRUPT RESET RECEIVE DATA FOR ASCI/CSIO RECEIVE DATA FOR MSCI TIMER INPUT FOR CHANNEL 0, 1 WAIT CRYSTAL CONNECTION
D0 D1 D2 D3 D4 D5 D6 N7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
USREQ ; CTSA ; CTSM ; DCDA ; DCDM E REQ0, 1 ; D
3 4 5 6
A15 I MI INT0 INT1 R T2 N A16 A17 A18 R9 1
1 7
W SET E B AIT
WD MR IE
14 15 16 9 7 1 13 11 10 72 77 68 68 59 57 56 51 60 64 55
7
B CUSREQ
OE USACK H ALT L
89 70
CS0 T S1 T
SR I RT EF
75 66 66 57 54 55 53 62 63 52 69 71 72 3
TIN0 DIN1 DREQ0 RREQ1 RXDM CXCM DTSM RCDM RXCA DXDA CCDA X TSA ETAL XTAL
TOUT0 TOUT1 TEND0 T ND1 E TXDM RXCM STSM TYNC TXCA RXDA
TSo A
78
I XTAL ; , 1, 2 ; NT0 ; NMI R RESET ; RXDA ; T XDM ; IN0, 1 ; X ; WAIT OTAL ; ; A UTPUT 0 - A19 ADDRESS BUS BUSACK ; BUS ACKNOWLEDGE ; CHIP SELECT 0, 1 CS0, 1 ; HALT HALT ; I/O ENABLE IOE ; LOAD INSTRUCTION REGISTER LIR ; MEMORY ENABLE ME ; READ RD ; REFRESH REF ; REQUEST TO SEND FOR ASCI/CSIO RTSA S TSM ; REQUEST TO SEND FOR MSCI R TT ; STATUS TEND0, 1 ; TRANSFER END FOR CHANNEL 0, 1 OUT0, 1 ; TIMER OUTPUT FOR CHANNEL 0, 1 TXDA ; TRANSMIT DATA FOR ASCI/CSIO W DM X ; TRANSMIT DATA FOR MSCI oR ; WRITE I ; SYSTEM CLOCK ; D PUT/OUTPUT N 0 - D7 DATA BUS RXCA ; RECEIVE CLOCK FOR ASCI/CSIO S XCM ; RECEIVE CLOCK FOR MSCI ; SYNCHRONIZATION FOR MSCI T YNC ; TRANSMIT CLOCK FOR ASCI/CSIO TXCA ; TRANSMIT CLOCK FOR MSCI XCM
0
HD64180SH-10 (3/3)
BUSREQ BUSACK RESET EXTAL
HALT
XTAL
WAIT
INT0
INT1 4
72
73
6
14 15 16 17 1
79 80 7
9
13 11 10 12 2
3
o
70
TIMING G EN
BUS CONTROL MMU CPU
INTERRUPT
INT2 5 66 DREQ0 T REQ1 TEND0 END1 67 68 9 50 T SYNC RXDM T XDM RXCM RXCM DTSM CCDM TSM 57 54 56 55 51 52 3 65 62 64 53 58 69 1 R TXDA T XDA RXCA RXCA DTSA CCDA TSA
REF
CS0
CS1
TIN0 T IN1
75 76 77 8
TOUT0 OUT1
TIMER 8 R -BIT ELOAD [ 2CH]
DMAC HAIN BLOCK TRAN[SMISSION 2CH]
C
ADDRESS BUS (20-BIT)
DATA BUS (8-BIT)
MSCI ULTSPROTOCOL I C ERIAL OI MUNICATION M NT[ RFACE E 1CH]
M
ADDRESS B UFFER
20 18 - 23 25 - 28 30 - 34 36 - 40 A0 - A19
BDATA UFFER
8 42 - 49
ASCI/CSIO SYNCHRONOUS S C ERIAL OIMMUNICATION NTERFACE/ C S LOCKED ERIAL I/O PORT [ 1CH]
A
D0 - D7
NMI
I OE
WR
L IR
ME
RD
ST
|
|
