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Details, datasheet, quote on part number:HD64180ZF
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Datasheet text preview:
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C-MOS 8-BIT MICROPROCESSOR
- TOP VIEW 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 NC NC NC NC NC
HD64180ZF (1/3) IL08
GND
NC NC
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC NC
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
GND GND GND NC V DD (+5V) NC
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
(V DD =+5V) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O I I I I O O O O O O O O O O O O SIGNAL NMI NC NC INT0 INT1 INT2 ST A0 A1 A2 A3 GND A4 NC A5 A6 A7 A8 A9 A10 PIN No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O O O O O O O O O O I/O I/O I/O I/O I/O I/O SIGNAL A11 NC NC A12 A13 A14 A15 A16 A17 NC A18/TOUT V DD A19 GND D0 D1 D2 D3 D4 D5 PIN No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 I/O I/O I /O O I I O I I/O O SIGNAL D6 NC NC D7 RTS0 CTS0 DCD0 TXA0 RXA0 CKA0/DREQ0 NC TXA1 TEST RXA1 CKA1/TEND0 TXS RXS/CTS1 CKS DREQ1 TEND1 PIN No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O O O O O O O O O O I I I O I I SIGNAL HALT NC NC REF IOE ME E LIR WR RD GØ ND GND XTAL NC EXTAL WAIT BUSACK BUSREQ RESET
I I/O O I I/O I O
HD64180ZF (2/3) 35 36 37 38 39 40 41 44 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18/TOUT A19 IOE ME E WR RD BUSREQ 8 9 10 11 13 15 16 17 18 19 20 21 24 25 26 27 28 29 31 33 65 66 67 69 70 78 7 61 64 68 0-A19 BUSACK BUSREQ CKA0, 1 CKS CTS0, 1 ADDRESS BUS (3-STATE) ; BUS ACKNOWLEDGE ; BUS REQUEST ; CLOCK FOR ASYNCHRONOUS SCI CHANNEL 0, 1 ; CLOCK FOR SERIAL I/O PORT ; CLEAR TO SEND FOR ASYNCHRONOUS SCI CHANNEL 0, 1 D0-D7 ; DATA BUS DCD0 ; DATA CARRIER DETECT FOR ASYNCHRONOUS SCI CHANNEL 0 DREQ0,1 ; DMA REQUEST FOR CHANNEL 0, 1 E ; ENABLE EXTAL ; EXTERNAL CLOCK INT0-2 ; INTERRUPT 0-2 IOE ; I/O ENABLE (3-STATE) LIR ; LOAD INSTRUCTION REGISTER ME ; MEMORY ENABLE (3-STATE) NMI ; NON-MASKABLE INTERRUPT RD ; READ REF ; REFRESH RTS0 ; REQUEST TO SEND FOR ASYNCHRONOUS SCI CHANNEL 0 RXA0, 1 ; RECEIVE DATA FOR ASYNCHRONOUS SCI CHANNEL 0, 1 RXS ; RECEIVE DATA FOR SERIAL I/O PORT ST ; STATUS TEND0, 1 ; TRANSFER END FOR CHANNEL 0, 1 TOUT ; TIMER OUT TXA0,1 ; TRANSFER DATA FOR ASYNCHRONOUS SCI CHANNEL 0, 1 TXS ; TRANSFER DATA FOR SERIAL I/O PORT WR ; WRITE (3-STATE) Ø ; SYSTEM CLOCK
1 NMI 4 INT0 5 INT1 6 INT2 80 RESET
77
WAIT
79
BUSACK ST HALT REF 50 CKA0/DREQ0 LIR 55 CKA1/TEND0 59 DREQ1 46 47 49 54 57 58 CTS0 DCD0 RXA0 RXA1 RXS/CTS1 CKS TEND1
60
45 RTS0 48 TXA0 52 TXA1 56 TXS Ø 71 A
74 XTAL 76 EXTAL
HD64180ZF (3/3) 1 NMI 4 INT0 5 INT1 6 INT2 WAIT BUSREQ RESET BUSACK ST HALT REF IOE ME E LIR WR RD 77 79 80 78 7 61 64 65 66 67 68 69 70
INTERRUPT
MU
ADDRESS BUFFER
8-29 A0-A17, A19
16-BIT PROGRAMMABLE RELOAD TIMERS (2)
31
A18/TOUT
CPU BUS STATE CONTROL
DATA BUFFER
25-44 D0-D7
ADDRESS BUS (16-BIT)
DATA BUS (8-BIT)
ASYNCHRONOUS SCI (CHANNEL 0)
46 47 49 45 48 50
CTS0 DCD0 RXA0 RTS0 TXA0 CKA0/DREQ0
74 XTAL 76 EXTAL 71 Ø
TIMING GENERATOR
DMACS (2) M
59 DREQ1 60 TEND1
ASYNCHRONOUS SCI (CHANNEL 1)
55 CKA1/TEND0 54 RXA1 52 TXA1
CLOCKED SERIAL I/O PORT
57 RXS/CTS1 58 CKS 56 TXS
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