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Part: ICX088
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Datasheet: Download ICX088 datasheet File size : 421 kB
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ICX088AK
1/4-inch CCD Image Sensor for NTSC Color Video Cameras
Description The ICX088AK is an interline CCD solid-state image sensor suitable for NTSC color digital video cameras. This chip supports DV standard SD mode, and can drive at 13.5MHz. High sensitivity, wide dynamic range and low dark current are achieved through the adoption of Super HAD CCD technology. In addition, high resolution is achieved through the adoption of Ye, Cy, Mg and G complementary color mosaic filters. This chip features a field period readout system and an electronic shutter with variable charge-storage time. The package is a 14-pin DIP (Plastic), and both top and bottom surface reference can be assured at the same time. 14 pin DIP (Plastic)
in 1 2
V
Features 12 · Supports DV standard SD mode (13.5MHz) 2 · High resolution, high sensitivity and wide dynamic range 40 H Pin 8 · Low dark current and low smear · Excellent antiblooming characteristics Optical black position · Supply voltage: 12V (Top View) · Horizontal register drive amplitude: 2.7 to 3.6V · No voltage adjustment (Reset gate and substrate bias are not adjusted.) · Continuous variable-speed shutter · Recommended range of exit pupil distance: 20 to 100mm · Ye, Cy, Mg and G complementary color mosaic filters on chip · 14-pin high precision plastic package (both top and bottom surface reference possible) Device Structure · Interline CCD image sensor · Optical size: · Total number of pixels: · Total number of effective pixels: · Chip size: · Unit cell size: · Optical black: · Number of dummy bits: · Substrate material:
P
1/4-inch format 766 (H) × 508 (V) approx. 390K pixels 724 (H) × 494 (V) approx. 360K pixels 4.60mm (H) × 3.97mm (V) 5.05µm (H) × 5.55µm (V) Horizontal (H) direction: Front 2 pixels, rear 40 pixels Vertical (V) direction: Front 12 pixels, rear 2 pixels Horizontal 20 Vertical 1 (even fields only) Silicon
Super HAD CCD is a trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly
developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E97707-PS
ICX088AK
VOUT
GND
VL
V1
V 2
V3
7
6
5
Cy
4
Ye G Ye Mg Ye G
3
Cy Mg Cy G Cy Mg
2
Ye G Ye Mg Ye G
Vertical Register
Mg Cy G Cy Mg
Horizontal Register Note) 8 9 10 11 12 13 14 : Photo sensor
Pin Description Pin No. Symbol 1 2 3 4 5 6 7 V4 V3 V2 V1 VL GND VOUT Description
S UB
CSUB
GND
Pin No. Symbol 8 9 10 11 12 13 14 VDD GND SUB CSUB RG H1 H2
RG
VDD
H 2
H1
V4
1 Note)
Block Diagram and Pin Configuration (Top View)
Description Supply voltage GND Substrate clock Substrate bias 1 Reset gate clock Horizontal register transfer clock Horizontal register transfer clock
Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Protective transistor bias GND Signal output
1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. Absolute Maximum Ratings Item VDD, VOUT, RG SUB V1, V3 SUB Against SUB V2, V4, VL SUB H1, H2, GND SUB CSUB SUB VDD, VOUT, RG, CSUB GND Against GND V1, V2, V3, V4 GND H1, H2 GND Against VL V1, V3 VL V2, V4, H1, H2, GND VL Voltage difference between vertical clock input pins Between input clock pins Storage temperature Operating temperature 2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. 2 H1 H2 H1, H2 V4 Ratings 40 to +8 50 to +15 50 to +0.3 40 to +0.3 25 to 0.3 to +18 10 to +18 10 to +5 0.3 to +28 0.3 to +15 to +15 5 to +5 13 to +13 30 to +80 10 to +60 Unit Remarks V V V V V V V V V V V V V °C °C 2
ICX088AK
Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock Symbol VDD VL SUB RG Min. 11.64 Typ. 12.0 1 2 2 Max. 12.36 Unit V Remarks
1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. 2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Supply current Symbol IDD Min. Typ. 5.0 Max. Unit mA Remarks
Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VV Vertical transfer clock voltage VVH3 VVH VVH4 VVH VVHH VVHL VVLH VVLL Horizontal transfer clock voltage Reset gate clock voltage VH VHL VRG VRGLH VRGLL VRGL VRGLm Substrate clock voltage VSUB 17.3 18.5 2.7 0.05 2.7 3.3 0 3.3 Min. 11.64 0.05 0.2 6.85 5.95 0.25 0.25 Typ. 12.0 0 0 6.5 6.5 Max. 12.36 0.05 0.05 6.15 6.9 0.1 0.1 0.3 0.3 0.3 0.3 3.6 0.05 3.6 0.4 0.5 19.3 Unit V V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 Low-level coupling Low-level coupling High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL3 + VVL4)/2 VV = VVHn VVLn (n = 1 to 4) VVH = (VVH1 + VVH2)/2 Remarks
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