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Details, datasheet, quote on part number:ICX204
 
 
Part:ICX204
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Datasheet:Download ICX204 datasheet   File size : 299 kB
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Datasheet text preview:
ICX204AK
1/3-inch Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras Preliminary
Description The ICX204AK is a 1/3-inch optical interline CCD solid-state image sensor with a square pixel array and 800K effective pixels. Progressive scan allows all pixels' signals to be output independently within approximately 1/20 second. Also, the adoption of high frame rate readout mode supports 60 frames per second. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize full-frame still image without a mechanical shutter. High resolution and high color reproductivity are achieved through the use of R, G, B primary color mosaic filters. Further, high sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip is suitable for applications such as electronic still cameras, PC input cameras, etc. Features · Progressive scan allows individual readout of the image signals from all pixels. · High horizontal and vertical resolution (both approx. 600TV-lines) still image without a mechanical shutter. · Supports 60 frames per second mode · Square pixel · Maximum horizontal drive frequency: 20MHz · No voltage adjustments (reset gate and substrate bias are not adjusted.) · R, G, B primary color mosaic filters on chip · High resolution, high color reproductivity, high sensitivity, low dark current · Low smear, excellent antiblooming characteristics · Continuous variable-speed shutter · Recommended range of exit pupil distance: ­20 to ­100mm Device Structure · Interline CCD image sensor · Optical size: · Total number of pixels: · Number of effective pixels: · Number of active pixels: · Chip size: · Unit cell size: · Optical black: · Number of dummy bits: · Substrate material: 16 pin DIP (Plastic)
in 1 2
V
3 Pin 9 H
P
7 40
Optical black position (Top View)
1/3-inch format 1077 (H) × 788 (V) approx. 850K pixels 1034 (H) × 779 (V) approx. 800K pixels 1024 (H) × 768 (V) approx. 790K pixels (5.952mm diagonal) 5.80mm (H) × 4.92mm (V) 4.65µm (H) × 4.65µm (V) Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 7 pixels, rear 2 pixels Horizontal 29 Vertical 1 Silicon
Wfine CCD is a trademark of Sony Corporation. Represents a CCD adopting progressive scan, primary color filter and square pixel. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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PE97X05-PS
ICX204AK
Block Diagram and Pin Configuration (Top View)
VOUT GND GND GND V2A V2B
2
G B G B G B G
8
7
6
5
V1
4
3
R
G B G B G B G
R G R G R G R
Vertical register
G R G R G R
Horizontal register Note) 9 10 11 12 13 14 15 16 : Photo sensor
Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol V3 V2B V1 V2A GND GND GND VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND GND GND Signal output Pin No. 9 10 11 12 13 14 15 16 Symbol VDD GND SUB CSUB VL RG H1 H2 Description Supply voltage GND Substrate clock Substrate bias1 Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock
1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF.
SUB
CSUB
GND
­2­
RG
VDD
H2
H1
VL
V3
1 Note)
ICX204AK
Absolute Maximum Ratings Item VDD, VOUT, RG ­ SUB V2A, V2B ­ SUB Against SUB V1, V3, VL ­ SUB H1, H2, GND ­ SUB CSUB ­ SUB VDD, VOUT, RG, CSUB ­ GND Against GND V1, V2A, V2B, V3 ­ GND H1, H2 ­ GND Against VL V2A, V2B ­ VL V1, V3, H1, H2, GND ­ VL Voltage difference between vertical clock input pins Between input clock pins H1 ­ H2 H1, H2 ­ V3 Ratings ­40 to +10 ­50 to +15 ­50 to +0.3 ­40 to +0.3 ­25 to ­0.3 to +18 ­10 to +18 ­10 to +5 ­0.3 to +28 ­0.3 to +15 to +15 ­5 to +5 ­13 to +13 ­30 to +80 ­10 to +60 Unit Remarks V V V V V V V V V V V V V °C °C 2
Storage temperature Operating temperature 2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
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