|Datasheet||Download M28F420 datasheet
± 10% SUPPLY VOLTAGE ± 10% PROGRAMMING VOLTAGE FAST ACCESS TIME: 60ns PROGRAM/ERASE CONTROLLER (P/E.C.) AUTOMATIC STATIC MODE MEMORY ERASE in BLOCKS Boot Block (Bottom location) with hardware write and erase protection Parameter and Main Blocks 100,000 PROGRAM/ERASE CYCLES LOW POWER CONSUMPTION 20 YEARS DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code: 00FAh
G W BYTE WP RP VPP VCC VSS Address Inputs Data Input / Outputs Data Input / Outputs Data Input/Output or Address Input Chip Enable
Output Enable Write Enable Byte/Word Organization Write Protect Reset/Power Down/Boot Block Unlock Program & Erase Supply Voltage Supply Voltage Ground
Parameter Ambient Operating Temperature Under Bias Storage Temperature Input or Output Voltages Supply VoltageA9, RP Voltage Program Supply Voltage, during Erase or Programming
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns. 3. Maximum Voltage may overshoot to 7V during transition and for less than 20ns. 4. Depends on range.
DESCRIPTION The M28F420 Flash memory is a non-volatile memory that may be erased electrically at the block level and programmed by byte or by word. The interface is directly compatible with most microprocessors. It is offered in SO44 package. Organization The organization, x16, is selectable by an external BYTE signal. When BYTE is Low the x8 organization is selected, the Data Input/Output signal DQ15 acts as Address line A1 and selects the lower or upper byte of the memory word for output DQ0-DQ7, DQ8-DQ14 remain high impedance. When BYTE is High the memory uses the Address inputs A0-A17 and the Data Input/Outputs DQ0-DQ15. Memory control is provided by Chip Enable, Output Enable and Write Enable inputs. A Reset/Power Down/Boot block unlock, tri-level input, places the memory in deep power down, normal operation. Memory Blocks Erasure of the memory is in blocks. There are 7 blocks in the memory address space, one Boot Block of 16 Kbytes or 8 Kwords, two 'Key Parameter Blocks' of 8 Kbytes or 4 Kwords, three 'Main Blocks' of 96 Kbytes or 48 Kwords, and one 'Main Block' of 128 Kbytes or 64 Kwords. The M28F420 locates the Boot Block starting at the bottom (00000h). The blocks mapping is shown in Figure 3. Each block of the memory can be erased separately over typically 100,000 times and erasure takes typically 1 second. The Boot Block is hardware protected from accidental programming or erasure, depending on the RP and WP signals. Program/Erase commands in the Boot Block are
M28F420 BOTTOM BOOT BLOCK 3FFFFh 64K MAIN BLOCK 2FFFFh 64K MAIN BLOCK 1FFFFh 64K MAIN BLOCK 0FFFFh 48K MAIN BLOCK 03FFFh 4K PARAMETER BLOCK 02FFFh 4K PARAMETER BLOCK 01FFFh 8K BOOT BLOCK 00000hTable 3. Memory Blocks Protection Truth Table
VPP VPPL VPPH V IL VIH VHH WP X VIL VIH X Boot Block Protected Unprotected Other Blocks Protected Unprotected
executed only when is at VHH is at VIH (while is at VIH). The memory blocks protection scheme is shown in Table 3. Block erasure may be suspended in order to read data from other blocks of the memory, and then resumed. Programming and erasure of the memory blocks is disabled when the program supply is at VPPL. Bus Operations Six operationscan be performedby theappropriate bus cycles, Read Byte or Word from the Array,
Read Electronic Signature, Output Disable, Standby, Power Down and Write the Command of an Instruction. Command Interface Commands can be written to a CommandInterface (C.I.) latch to perform read, programming, erasure and to monitor the memory's status. When power is first applied, on exit from power down or if VCC falls below VLKO, the command interface is reset to Read Memory Array.
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