|Datasheet||Download MC14006BD datasheet
The MC14006B shift register is comprised of four separate shift register sections sharing a common clock: two sections have four stages, and two sections have five stages with an output tap on both the fourth and fifth stages. This makes it possible to obtain a shift register or 18 bits by appropriate selection of inputs and outputs. This part is particularly useful in serial shift registers and time delay circuits. Output Transitions Occur on the Falling Edge of the Clock Pulse Fully Static Operation Can be Cascaded to Provide Longer Shift Register Lengths Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range PinforPin Replacement for CD4006B MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter VDD Vin, Vout lin, lout PD Tstg TL DC Supply Voltage Value L SUFFIX CERAMIC CASE 632
Unit 0.5 to Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature + 150
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From To 125_C Ceramic "L" Packages: 12 mW/_C From To 125_CD+1 C #Inverter used only on the first stage of each fourstage element.
Input to output is (A) A bidirectional low impedance when control input 1 is "low" and control input 2 is "high". (B) An open circuit when control input 1 is "high" and control input 2 is "low".©MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA
* The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. When shift register sections are cascaded, the maximum rise and fall times of the clock input should be equal to or less than the rise and fall times of the data outputs driving data inputs, plus the propagation delay of the output driving stage for the output capacitance load.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.Figure 1. Typical Output Source Current Characteristics Test Circuit
Figure 2. Typical Output Sink Current Characteristics Test Circuit
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