|Datasheet||Download MC14016 datasheet
The MC14016B quad bilateral switch is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. Each MC14016B consists of four independent switches capable of controlling either digital or analog signals. The quad bilateral switch is used in signal gating, chopper, modulator, demodulator and CMOS logic implementation. Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Linearized Transfer Characteristics Low Noise 12 nV/Cycle, f 1.0 kHz typical PinforPin Replacements for CD4016B, CD4066B (Note improved transfer characteristic design causes more parasitic coupling capacitance than CD4016) For Lower RON, Use The HC4016 HighSpeed CMOS Device or The MC14066B This Device Has Inputs and Outputs Which Do Not Have ESD Protection. Antistatic Precautions Must Be Taken. MAXIMUM RATINGS* (Voltages Referenced to VSS)Symbol Parameter VDD Vin, Vout lin Isw PD DC Supply Voltage L SUFFIX CERAMIC CASE 632
Value Unit 0.5 to Input or Output Voltage (DC or Transient) Input Current (DC or Transient), per Control Pin Switch Through Current Storage Temperature 0.5 to VDD ± 25 Power Dissipation, per Package 260 mW Tstg + 150
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From To 125_C Ceramic "L" Packages: 12 mW/_C From To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.©MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA
Characteristic Figure 1 Symbol VIL VDD Vdc 25_C 125_C Min Max Min Typ Max 0.9 Min Max Unit Vdc Input Voltage Control Input VIH 8.0 13 Vdc Input Current Control Input Capacitance Control Switch Input Switch Output Feed Through Iin µAdc pF Cin Quiescent Current (Per Package) 2,3 IDD µAdc "ON" Resistance (VC = VDD, 10 k) (Vin + 5.0 Vdc) (Vin 5.0 Vdc) VSS 5.0 Vdc (Vin ± 0.25 Vdc) (Vin + 7.5 Vdc) (Vin 7.5 Vdc) VSS 7.5 Vdc (Vin ± 0.25 Vdc) (Vin + 10 Vdc) (Vin + 0.25 Vdc) VSS = 0 Vdc (Vin + 5.6 Vdc) (Vin + 15 Vdc) (Vin + 0.25 Vdc) VSS = 0 Vdc (Vin + 9.3 Vdc) 4,5,6 RON Ohms "ON" Resistance Between any 2 circuits in a common package (VC = VDD) (Vin ± 5.0 Vdc, VSS 5.0 Vdc) (Vin ± 7.5 Vdc, VSS 7.5 Vdc) Input/Output Leakage Current (VC = VSS) (Vin + 7.5, Vout 7.5 Vdc) (Vin 7.5, Vout + 7.5 Vdc) RON Ohms µAdc NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. For voltage drops across the switch ( V switch) mV at high temperature), excessive V DD current may be drawn; i.e., the current out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.
Characteristic Figure 7 Symbol tPLH, tPHL VDD Vdc Min Typ Max Unit ns Propagation Delay Time (VSS = 0 Vdc) Vin to Vout (VC = VDD, 10 k) Control to Output (Vin 10 Vdc, k) 8 tPHZ, tPLZ, tPZH, tPZL ns Crosstalk, Control to Output (VSS = 0 Vdc) (VC = VDD, Rin 10 k, Rout = 1.0 kHz) mV Crosstalk between any two switches (VSS = 0 Vdc) (RL = 1.0 MHz, V crosstalk out1) Vout2 Noise Voltage (VSS = 0 Vdc) (VC = VDD, = 100 Hz) (VC = VDD, = 100 kHz) 80 dB nV/Cycle Second Harmonic Distortion (VSS 5.0 Vdc) (Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc, = 1.0 kHz) 0.16 % Insertion Loss (VC = VDD, Vin = 1.77 Vdc, VSS 5.0 Vdc, RMS centered = 0.0 Vdc, = 1.0 MHz) V Iloss 20 log10 out) Vin (RL 1.0 k) (RL 10 k) (RL 100 k) (RL 1.0 M) Bandwidth 3.0 dB) (VC = VDD, Vin = 1.77 Vdc, VSS 5.0 Vdc, RMS centered @ 0.0 Vdc) (RL 1.0 k) (RL 10 k) (RL 100 k) (RL 1.0 M) OFF Channel Feedthrough Attenuation (VSS 5.0 Vdc) Vout 50 dB) (VC = VSS, 20 log10 Vin (RL 1.0 k) (RL 10 k) (RL 100 k) (RL BW 5.0 MHz kHz #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
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