|Datasheet||Download MC14072BCP datasheet
|Cross ref.||Similar parts: CD4072BE|
The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. Supply Voltage Range = 3.0 Vdc to 18 Vdc All Outputs Buffered Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range. Double Diode Protection on All Inputs Except: Triple Diode Protection on MC14011B and MC14081B PinforPin Replacements for Corresponding CD4000 Series B Suffix Devices (Exceptions: MC14068B and MC14078B)
Quad 2-Input NOR Gate Dual 4-Input NOR Gate Quad 2-Input NAND Gate Dual 4-Input NAND Gate Triple 3-Input NAND Gate Triple 3-Input NOR Gate 8-Input NAND Gate Quad 2-Input OR Gate Dual 4-Input OR Gate Triple 3-Input AND Gate Triple 3-Input OR Gate 8-Input NOR Gate Quad 2-Input AND Gate Dual 4-Input AND Gate
Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature
TL Lead Temperature (8Second Soldering) _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From To 125_C Ceramic "L" Packages: 12 mW/_C From To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.İMOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA
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