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Part: MC145650PP2/D
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SEMICONDUCTOR TECHNICAL DATA
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The MC145650 is a single integrated circuit transceiver device for ANSI (American National Standard Institute) T1.413 category 2 ADSL modems1, based on the Discrete Multi-tone (DMT) line code. The category 2 specification requires payload rates of (6.144 Mbps + 640 kbps) downstream and 640 kbps upstream, with crosstalk, over carrier serving area (CSA) range loops, and to achieve (1.544 Mbps + 176 kbps) downstream and 176 kbps upstream with crosstalk, over selected ANSI integrated services digital network (ISDN) loops. The payload makeup is flexible thereby allowing multiple data streams to be multiplexed and demultiplexed. The MC145650 is capable of data rates up to 8 Mbps downstream and 1 Mbps bi-directionally, however actual rates obtained in any system are dependent on loop length, impairments, and transmitted power. The ADSL and DMT techniques are adaptive, changing system parameters based on loop characteristics in order to optimize the data rate. This device combined with a microcontroller and a line interface may be configured as either a central office ADSL transceiver unit (ATU-C) or as a remote terminal ADSL transceiver unit (ATU-R). An ADSL system could be configured to provide the user with high speed Internet access with POTS, or two 3 Mbps MPEG2 (or four 1.5 Mbps MPEG1) video channels, a 640 Kbps bi-directional data channel, along with POTS (Plain Old Telephone Service), all over existing copper telephone wire. · · · · · · · · · · · · · · · · · · Designed for ANSI Standard ANS T1.413 Category 2 modems (ETR328) Single Chip Integrated Transceiver for Reduced System Cost Single 3.3V ±5% Power Supply Estimated 2 Watt Power Dissipation Flexible Channel Multiplexing and Demultiplexing Framing and Deframing Central Office or Remote Configurable Maintenance Facilities Initialization Control CRC and Scrambling Interleaving Reed-Solomon Forward Error Correction Wei 4D Trellis Encoding and Decoding DMT Modulation and Demodulation DMT Echo Cancellation for ADSL A/D Conversion and Receive Path Filtering D/A Conversion and Transmit Path Filtering Adaptive Rate Mode (N x 32 kbps Channel Programmability)
1
144 PIN CQFP
Without 26 dBm transmit power boost
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1.6 03/97 TN97032000 © Motorola, Inc. 1997
FUNCTIONAL DESCRIPTION
All of the basic functions required to perform both the transmit and the receive operations in a category 2 ADSL modem are contained within the MC145650. These functions include those that make up the transmit and receive data processing as well as the control, timing and test functions that are outside the data path. A detailed functional block diagram of the MC145650 is shown in Figure 1.
Digital Interface Multiplex FEC Interleave TCM
DMT Processor DMT Modulator Echo Canceller Clip Mitigation
Analog Front End DAC Transmit Amplifier TXA Port
Digital Interface FIFOs and DPLLs
Digital Ports
External Line Interface ADC Receive Filter
Interleaver Memory Port
Demultiplex
FEC Deinterleave
Viterbi
DMT Demodulator
RXA Port
Host Microprocessor Interface Host
Crystal Oscillator/PLL Timing
Test Control Test
Control Port
Clock Port
JTAG
Figure 1. MC145650 Block Diagram Digital Interface
Input and output data is transferred through the MC145650 digital interface. The MC145650 can support up to seven independent data streams, or bearer services, on its digital ports. The digital ports include four simplex ports for transmitting data downstream (as from an ADSL unit in a Central office (CO) to an ADSL remote terminal or subscriber box), and three duplex ports for bidirectional data transfers. All three duplex ports may be reconfigured to provide upstream simplex channels. The digital interface also provides framing, deframing, trellis encoding/decoding, and data interleaving functions.
Interleaver Memory Port
The interleaver memory port provides address, data, and control lines for interfacing to a fast static RAM used for interleave storage.
DMT Processor
The DMT processor consists of an embedded DSP and peripherals that perform the modulation, demodulation, and echo cancellation for the system. Both transmit and receive data processing is handled by the DMT processor, via the Analog Front End (AFE) and the digital interface.
Table 1. Supported Port Rates.
Port A B C D E F G Type Simplex Simplex Simplex Simplex Duplex/Simplex Duplex/Simplex Duplex/Simplex Min. 32 kbps 32 kbps 32 kbps 32 kbps 16 kbps 32 kbps 32 kbps Max. 10.752 Mbps 4.608 Mbps 3.072 Mbps 2.048 Mbps 1.024 Mbps 1.024 Mbps 1.024 Mbps
Analog Front End (AFE)
The AFE performs the digital-to-analog conversions on the data samples received from the DMT processor and then provides the necessary filtering and signal conditioning for transmission on the line interface. During the receive operation, the AFE filters the analog input and then performs the analog-to-digital conversion, sending the digital samples on to the DMT processor.
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MC145650PP2/D
Host Processor Interface (HPI)
The host processor interface allows communication with the MC145650 by an external microprocessor. This interface is compatible with the 8-bit parallel data and address interface available on popular Motorola microcontrollers and allows the host processor to be connected directly to the MC145650. The HPI parallel interface contains an 8-bit data bus, a 5-bit address bus, a chip select and a read/write signal. The interface also provides a single interrupt line to allow the MC145650 to request interrupt service from the host processor. Depending on the application, this processor could be from the Motorola MC68302, MC68360, or MPC860 families.
Timing Block
System clocks for the MC145650 are generated by the timing block. Depending on the operating mode and the type of transceiver operating at the far end, the timing block will generate the high rate system clock from an externally supplied clock, or from the recovered timing from the received DMT pilot tone. The externally supplied clock may be provided directly or a crystal may be used to generate a local oscillator reference.
Test Block
The test block provides the control circuitry necessary to perform JTAG and special debug features.
PIN ASSIGNMENTS
Pinout for the MC145650 is shown in Figure 2 below.
MC145650
ADATA ACLK ADAV BDATA BCL K BDAV CDATA CCL K CDAV DDATA DCL K DDAV E1DATA E1DAV E1CLK E2DATA E2DAV E2CLK F1DATA F1DAV F1CLK F2DATA F2DAV F2CLK G1DATA G1DAV G1CLK G2DATA G2DAV G2CLK HVCC (2) HVSS (2) IVCC (4) IVSS (4) DVCC (4) DVSS (4) QVCC (4) QVSS (4) Port A TXP TXN RXP RXN RXG TXG HFB RXREFP RXREFN TXREFP TXREFN VCXO_REFP VCXO_REFN VAG XTALIN XTALOUT ID[7:0] IA[17:0] IR_NW ICS_L IOEN_L RESET_L HA[4:0] HD[7:0] HCS_ L HR_ NW HIRQ_L TCLK TMS T DI T DO TRST_L DE_ L TICMD(3) AVCC (5) AVSS (5) PVCC PVSS PVSS1 PCAP AVSS_SUB
Port B Analog Interface Port C
Port D Clocks
Port E
Interleaver Memory Port
Controls Port F Host Processor Interface
Port G JTAG Test Port
Digital Power
Analog Power
Figure 2. MC145650 Pin Assignments
MC145560PP2/D
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