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Part: MC44011D
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Advance Information Bus Controlled Multistandard Video Processor
The Motorola MC44011, a member of the MC44000 Chroma 4 family, is designed to provide RGB or YUV outputs from a variety of inputs. The inputs can be composite video (two inputs), SVHS, RGB, and color difference (RY, BY). The composite video can be PAL and/or NTSC as the MC44011 is capable of decoding both systems. Additionally, RY and BY outputs and inputs are provided for use with a delay line where needed. Sync separators are provided at all video inputs. In addition, the MC44011 provides a sampling clock output for use by a subsequent triple A/D converter system which digitizes the RGB/YUV outputs. The sampling clock (6.0 to 40 MHz) is phaselocked to the horizontal frequency. A d d i t i o n a l outputs include composite sync, vertical sync, field identification, luma, burst gate, and horizontal frequency. Control of the MC44011, and reading of status flags, is via an I2C bus. · Accepts NTSC and PAL Composite Video, SVHS, RGB, and RY, BY
MC44011
BUS CONTROLLED MULTISTANDARD VIDEO PROCESSOR
SEMICONDUCTOR TECHNICAL DATA
44 1
FN SUFFIX PLASTIC PACKAGE CASE 777 (PLCC)
· · · · · · · · ·
Includes Luma and Chroma Filters, Luma Delay Lines, and Sound Traps Digitally Controlled via I2C Bus RY, BY Inputs for Alternate Signal Source LineLocked Sampling Clock for A/D Converters Burst Gate, Composite Sync, Vertical Sync and Field Identification Outputs RGB/YUV Outputs can Provide 3.0 Vpp for A/D Inputs Overlay Capability Single Power Supply: 5.0 V, ±5%, 550 mW (Typical) 44 Pin PLCC and QFP Packages Representative Block Diagram
Outputs VCC1 Comp Video 1 Comp Video 2 Gnd1 Y1 RY BY 4 Input Select Sound Trap/Luma Filter/Luma Delay/ Chroma Filter/PAL and NTSC Decoder/Hue and Saturation Control
FB SUFFIX PLASTIC PACKAGE CASE 824E (QFP)
44 1
ORDERING INFORMATION
Device MC44011FN MC44011FB Operating Temperature Range TA = 0° to +70°C Package PLCC44 QFP
Inputs RY BY Y2 RGB Fast Comm
Color Difference Stage Contrast, Brightness, Saturation Control DACs Data Bus
R/V G/Y B/U VCC2 Gnd2
Outputs
Sync Separator Vertical Output Field ID 17.7 MHz Oscillator 14.3 MHz Filter PLL Burst Gate Vertical Decoder
Select 4
Sync Separator
MC44011
I2C Data Interface/ Registers PLL #2 Pixel Clock PLL/VCO
SDL SCL
To µP
PLL #1 Horizontal PLL/VCO
VCC3 Gnd3
16Fh/ CSync
Filter Switch
H Filter
Quiet Gnd
Fh Ref
15 k Ret
PLL Filter Frequency Divider
Clock
To A/D Converters
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Motorola, Inc. 1996
Rev 1
MOTOROLA ANALOG IC DEVICE DATA
1
Figure 1. Representative Block Diagram
Outputs In p u ts System Select Y1 Clamp 32 To Sync Sep Clamp Burst Ga te Clamp BY RY Signal Selection Y Blank 20 5 .0 Color Matrix and Controls 21 5 .0 22 B/U G/Y Ou tp u ts R/V BY RY B G R 5 .0 Clamp Clamp 23 C PAL/NTSC Decoder Ident BY RY Saturation/ Hue DACs VCC2 (5.0 V) Clamp Clamp 24 Gn d 2 Y1 33 BY 41 RY 42 RY 31 BY 30 Y2 29 B 26 G 27 R 28 FC 25 34 Ident Filter 43
2
Luma Delay C Chroma Trap & Luma Peaking C C Adj. Luma Delay X1, X2, X8 Fs Notch Chroma Filter ACC PAL/NTSC/SVHS Decoder Adaptive Sync Separator & Selector C From RGB & Y2 Inputs Sync Separator & Selector DACs Sync Separator Vertical Decoder 2Fh Comp Sync Bus Control & Flag Status Read 16Fh Line Counter & Decoder 525, 625 Coincidence Counter Vert. Sync Separator Saturation Contrast Blue Gain Red Gain Brightness Red DC Blue DC Color Difference Stage C PLL #1 16Fh Blank ÷ 64 2Fh Phase Det Calibration Circuit VCO PLL #2 Voltage Monitor U Phase & Frequency D Comparator Charge Pump 1240 MHz VCO ÷2 2Fo Fo I 2C Data Interface/ Registers 5 6 SCL SDL To µP 11 H Fil Quiet GND 16Fh/ S/C CSync 10 13 35 8 Burst Gate 14 Fh Ref Gnd3 17 15 15 k Ret 16 PLL #2 Filter Frequency Divider 18 Clock To A/D Converters 19 VCC3 (5.0 V)
Select
4.4/4.8/5.2 5.5/6.0/6.5 MHz
Comp Video 1 1
Comp Video 2 3
Sound Trap
ACC Filter
2
Chroma PLL Filter 44
PLL
17.7 MHz Xtal 1 38
Oscillator
MC44011
36 14.3 MHz Xtal 2
Field ID 7 5.0 V
Field ID
4
Vertical Sync
NC 37
5.0
I ref
9
VCC1 40 (5.0 V)
Figure 1.
Gnd1
39
12
MOTOROLA ANALOG IC DEVICE DATA
H Filt Switch
MC44011
ELECTRICAL CHARACTERISTICS (The tested electrical characteristics are based on the conditions shown in Table 1 and 2. Composite Video input signal = 1.0 Vpp, composed of: 0.7 Vpp BlacktoWhite; 0.3 Vpp SynctoBlack; 0.3 Vpp Color Burst. VCC1 = VCC2 = VCC3 = 5.0 V, Iref = 32 µA (Pin 9), unless otherwise noted.) Table 1. Control Bit Test Settings
Control Bit $777 $776 $775 $774 $773 $772 $771, 0 $787 $786 $797, 6 $7A7 $7A6 $7B7, 6 $7C7 $7C6, $7D6 $7D7, $7E7, 6 $7F7, 6, $806 $807 $817 $816 $827 $826 $837 $836 $847 $846 $857 $856 $867 $866 $877 $887 $886 Name SVHSY SVHSC FSI L2 GATE BLCP L1 GATE CB1, CA1 36/68 µs CalKill HI, VI Xtal SSD T1, T2 SSC SSA, SSB P1, P3, P2 D3, D1, D2 RGB EN Y2 EN Y1 EN YUV EN YX EN L2 Gain L1 Gain H Switch 525/625 Fosc ÷ 2 CSync Vin Sync H EN Y2 Sync V2/V1 RGB Sync Value 0 0 0 0 0 0 1,1 0 0 1,1 0 1,1 0 1, 1, 1 0, 0, 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 Composite Video input selected. Composite Video input selected. 50 Hz Field Rate selected. PLL #2 Gating enabled. Clamp Pulse Gating enabled. Vertical Gating enabled. Vertical section AutoCountdown mode Time from beginning of Line 4 to Vertical Sync is 36 µs. Horizontal Calibration Loop enabled. Normal 0 = 17.7 MHz crystal selected, 1 = 14.3 MHz crystal selected. Normal Sound Trap Notch filter set to 5.5 MHz (with 17.7 MHz crystal). Permits PAL and NTSC selection. 0, 1 = PAL decoding, 1,0 = NTSC decoding Sets Luma Peaking at 0 dB. Set Luma Delay to minimum Fast Commutate input can enable RGB inputs. Y2 input (Pin 29) deselected Y1 luma path from PAL/NTSC decoder selected. RGB output mode selected Disable luma matrix from RGB inputs. Set PLL #2 Phase/Frequency detector gain high. Set PLL #1 Phase Detector gain high. Set Horizontal Phase Detector filter switch open. 0 = 625 lines (PAL), 1 = 525 lines (NTSC) Select direct VCO output from PLL #2. 16 Fh output selected at Pin 13. Composite Video inputs (Pin 1 or 3) Sync Source selected. Enabled Horizontal Timebase. Y2 sync source not selected. Select Video 1 input (Pin 1). RGB inputs Sync Source not selected. Function
Table 2. DAC Test Settings
DAC $78 $79 $7D $7E $7F $80 $81
NOTE:
Value 32 32 00 00 63 32 32
Function RY/BY Gain Sub Carrier Phase Blue Output DC Bias Red Output DC Bias Pixel Clock VCO Gain Blue Contrast Trim Main Contrast
DAC $82 $83 $84 $85 $86 $87 $88
Value 32 32 32 32 32 16 32
Function Red Contrast Trim Blue Brightness Trim Main Brightness Red Brightness Trim Saturation (Color Diff.) Saturation (Decoder) Hue
Currents out of a pin are designated , and those into a pin are designated +.
MOTOROLA ANALOG IC DEVICE DATA
3
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