Details, datasheet, quote on part number: MC44461B
PartMC44461B
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Features, Applications

The MC44461 Picture­in­Picture (PIP) controller is a member of Motorola's low cost PIP family. It is NTSC compatible and contains all the analog signal processing, control logic and memory necessary to provide for the overlay of a small picture from a second non synchronized source onto the main picture of a television. All control and setup of the MC44461 is via a standard two pin I2C bus interface. The device is fabricated using BICMOS technology. It is available a 56­pin shrink dip (SDIP) package. The main features of the MC44461 are:

Two NTSC CVBS Inputs Switchable Main and PIP Video Signals Single NTSC CVBS Output Allows Simple TV Chassis Integration Two PIP Sizes; 1/16 and 1/9 Screen Area Freeze Field Feature Variable PIP Position by 64­Y Steps PIP Border with Programmable Color Programmable PIP Tint and Saturation Control Automatic Main to PIP Contrast Balance Vertical Filter Integrated 64 k Bit DRAM Memory Resulting in Minimal RFI Minimal RFI Allows Simple Low Cost Application into TV I2C Bus Control ­ No External Variable Adjustments Needed Operates from a Single 5.0 V Supply Economical 56­Pin Shrink DIP Package

Device MC44461B B SUFFIX PLASTIC PACKAGE CASE 859 (SDIP)

For surface mount package availability, contact your local Motorola sales office or authorized distributor.

This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA ANALOG IC DEVICE DATA

Rating Symbol VDD VCC VIR IO Value Unit V Power Supply Voltage Power Supply Voltage Input Voltage Range Output Current +6.0 ­0.5, VDD mA Power Dissipation Maximum Power Dissipation @ 70°C Thermal Resistance, Junction­to­Air Junction Temperature (Storage and Operating)

ELECTRICAL CHARACTERISTICS (VCC = VDD = 25°C, unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit POWER SUPPLY Total Supply (Pins 15, 43 and 50) Total ISupply 160 mA VIDEO Composite Video Input (Pin or 36) CVi Vpp Vdc dB Composite Video Output (Pin 49, Unterminated) Video Output DC Level (Sync Tip) Video Gain Video Frequency Response (Main Video to ­1.0 dB) Color Bar Accuracy MHz deg ±4.0 55 Video Crosstalk 75% Color Bars) Main to PIP to Main Output Impedance ­ 5.0 HORIZONTAL TIMEBASE Free Run HPLL Frequency (Pin 16) HPLL Pull­In Range HPLL Jitter Hz ns Burst Gate Timing (from Trailing Edge Hsync, Pin 24) Burst Gate Width µs VERTICAL TIMEBASE Vertical Countdown Window H lines µs Vertical Sync Integration Time ANALOG TO DIGITAL CONVERTER Resolution Bits Integral Non­Linearity ±1 LSB Differential Non­Linearity +2/­1 1.0 ADC ­ Y Frequency Response ­5.0 dB MHz kHz ADC U, V Frequency Response ­5.0 dB Sample Clock Frequency (4/3 FSC) 200 4.773 MHz

ELECTRICAL CHARACTERISTICS (continued) (VCC = VDD = 25°C, unless otherwise noted.)

DIGITAL TO ANALOG CONVERTER Resolution Bits Integral Non­Linearity ±1 LSB Deg dB Differential Non­Linearity +2/­1 ±10 Tint DAC Control Range (in 64 Steps) Saturation DAC Control Range (in 64 steps) ±6.0 NTSC DECODER Color Kill Threshold dB Threshold Hysteresis ACC (Chroma Amplitude Change, to ­12 dB) PIP CHARACTERISTICS PIP Size 1/9 Screen Horizontal 1/9 Screen Vertical 1/16 Screen Horizontal 1/16 Screen Vertical Border Size Horizontal Border Size Vertical pels lines pels lines pels lines Output PEL Clock (4 FSC) 14.318 100 MHz % Position Control Range Horizontal of Main Picture), 64 Steps Position Control Range Vertical of Main Picture), 64 Steps

Low Pass Filter Band Pass Filter Y NTSC Decoder
This device contains approximately 500,000 active transistors.

 

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