Details, datasheet, quote on part number: MC44817D
PartMC44817D
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Features, Applications

The MC44817/17B are tuning circuits for TV and VCR tuner applications. They contain on one chip all the functions required for PLL control of a VCO. The integrated circuits also contain a high frequency prescaler and thus can handle frequencies to 1.3 GHz. The MC44817 has programmable 512/1024 reference divider while the MC44817B has a fixed reference divider of 1024. The MC44817/17B are manufactured on a single silicon chip using Motorola's high density bipolar process, MOSAICTM (Motorola Oxide Self Aligned Implanted Circuits).

Complete Single Chip System for MPU Control (3­Wire Bus). Data and Clock Inputs are IIC Bus Compatible Divide­by­8 Prescaler Accepts Frequencies to 1.3 GHz 15 Bit Programmable Divider Accepts Input Frequencies to 165 MHz Reference Divider: Programmable for Division Ratios 512 and 1024. The MC44817B has a Fixed 1024 Reference Divider Tri­State Phase/Frequency Comparator Operational Amplifier for Direct Tuning Voltage Output (30 V) Four Integrated PNP Band Buffers for 14.4 V) Output Options for the Reference Frequency and the Programmable Divider Bus Protocol for or 19 Bit Transmission Extra Protocol for 34 Bit for Test and Further Features High Sensitivity Preamplifier Circuit to Detect Phase Lock Fully ESD Protected

Bands Out 20 k Fout Fref Test Logic DTB1 Gnd 9 T6 P­On Reset DTB2 POR EN Data Clock 2 3­Wire Bus Receiver CL Data RL DTF 4 Shift Register 15 Bit 15 Latches A Osc Latches B Preamp 1 HF Input 8 ÷8 Prescaler Program Divider 15 Bit Latch Control 3 XTAL B1 B0 Buffers Latches T3 T5 Latches Fout Fref 2.7 V Operational Amplifier Phase Comp Amp In VTUN VCC2 6

Preamp 2 This device contains 3,204 active transistors.

Rating Power Supply Voltage (VCC1) Band Buffer "Off" Voltage Band Buffer "On" Current Band Buffer ­ Short Circuit Duration to VCC3) (Note 2) Operational Amplifier Power Supply Voltage (VCC2) Operational Amplifier Short Circuit Duration to VCC2) Power Supply Voltage (VCC3) Storage Temperature Operating Temperature Range Band Buffer Operation (Note 50 mA each Buffer All Buffers "On" Simultaneously Operational Amplifier Output Voltage RF Input Level (10 MHz to 1.3 GHz)

Characteristic VCC1 Supply Voltage Range VCC1 Supply Current V) VCC2 Supply Voltage Range VCC2 Supply Current (Output Open) Band Buffer Leakage Current when "Off" 12 V Band Buffer Saturation Voltage when "On" 30 mA Band Buffer Saturation Voltage when "On" 40 mA only for to 80°C Data/Clock/Enable Current 0 V Data/Clock/Enable Current 5.0 V Data/Clock/Enable Input Voltage Low Data/Clock/Enable Input Voltage High Clock Frequency Range Oscillator Frequency Range Operational Amplifier Internal Reference Voltage Operational Amplifier Input Current DC Open Loop Voltage Gain Bandwidth Product (CL = 1.0 nF) Vout Low, Sinking 50 µA Vout High, Sourcing 10 µA, VCC2 ­ Vout Phase Comparator Tri­State Current Charge Pump High Current of Phase Comparator Charge Pump Low Current of Phase Comparator VCC3 Supply Voltage Range VCC3 Supply Current All Buffers "Off" One Buffer "On" when Open One Buffer "On" 40 mA Pin Min VCC1 Typ Max Unit µA V kHz MHz V nA V/V MHz V mA

Data Format and Bus Receiver The circuit is controlled a 3­wire bus via Data (DA), Clock (CL), and Enable (EN) inputs. The Data and Clock inputs may be shared with other inputs on the IIC­Bus while the Enable is a separate signal. The circuit is compatible with 18 and 19 bit data transmission and also has a mode for 34 bit transmission for test and additional features. The 3­wire bus receiver receives data for the internal shift register after the positive going edge of the EN­signal. The data is transmitted to the band buffers on the negative going edge of the clock pulse 4 (signal DTB1). 18 and 19 Bit Data Transmission The programmable divider may receive 14 bit (18 bit transmission) or 15 bit (19 bit transmission). The data is transmitted to the programmable divider (latches A) on the negative going edge of clock pulse or on the negative edge of the EN­signal if EN goes down after the 18th clock pulse (signal DTF). If the programmable divider receives 14 bit, its MSB (bit N14) is internally reset. The reset pulse is generated only if EN goes negative after the 18th clock pulse (signal RL).

34 Bit Data Transmission (For Test and Additional Features) In the test mode, the programmable divider receives 15 bit and the data is transferred to latches A on the negative edge of clock pulse 19 (signal DTF). The information for test is received on clock pulses to 26 and transmitted to the latches on the negative edge of pulse 34 (signal DTB2). These latches have a power­on reset. The power­on reset sets the programmable divider to a counting ratio 256 or higher and resets the corresponding latches to the test bits to T6 (signal POR). The bus receiver is not disturbed if the data format is wrong. Useless bits are ignored. If for example the Enable signal goes low after the clock pulse 9, bits one to four are accepted as valid buffer information and the other bits are ignored. If more than 34 bits are received, bit 35 and the following are ignored. Lock Detector The lock­detector output is low in lock. The output goes immediately high when an unlock condition is detected. The output goes low again when the loop is in lock during a complete period of the reference frequency.


 

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