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Details, datasheet, quote on part number:NM25C041LZ
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Datasheet text preview:
NM25C041 4096-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
February 1999
NM25C041 4096-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPITM) Synchronous Bus)
General Description
The NM25C041 is a 4096-bit MODE 1 SPI (Serial Peripheral Interface) CMOS EEPROM which is designed for high-reliability non-volatile data storage applications. The SPI interface features a byte-wide format (all data is transferred in 8-bit words) to interface with the Motorola 68HC11 microprocessor, or equivalent, at a 2.1MHz clock transfer rate. (This interface is considered the fastest serial communication method.) This 4-wire SPI interface allows the end user full EEPROM functionality while keeping pin count and space requirements low for maximum PC board space utilization. The SPI interface requires four I/O pins on each EEPROM device: Chip Select (CS), Clock (SCK), Serial Data In (SI), and Serial Data Out (SO), as well as 2 other control pins: Write Protect (WP) and HOLD (HOLD). The Write Protect pin can be used to disable the Write operation and the HOLD pin is used to interrupt the SI datastream and place the device in a Hold state during microprocessor instruction generation. Please refer to the following diagrams and description for more details. All programming cycles are completely self-timed and do not require an ERASE, or similar setup, before programming any cells. Programming can be performed in 3 modes, address (byte) write, page (16 addresses/bytes) write or partial page write. Furthermore, the EEPROM is provided with 4 levels of write protection wherein the data, once programmed, cannot be altered. This is controlled by the Status Register and is described in greater detail within this datasheet. In order to prevent spurious programming, the EEPROM has both a Write Enable command, which is immediately disabled after each programming operation, and a Write Protect (WP) pin, which must be pulled HIGH to program.
Features
s 2.1 MHz clock rate @ 2.7V to 5.5V s 4096 bits organized as 512 x 8 s Multiple chips on the same 3 wire bus with separate chip select lines s Self-timed programming cycle s Simultaneous programming of 1 to 4 bytes at a time s Status register can be polled during programming to monitor RDY/BUSY s Both the Write Protect (WP) pin and 'auto-write disable after programming' provides hardware and software write protection s Block write protect feature to protect against accidental writes s Endurance: 1,000,000 data changes s Data retention greater than 40 years s Packages available: 8-pin DIP and 8-pin SO
Block Diagram
CS HOLD SCK SI Instruction Register Instruction Decoder Control Logic and Clock Generators VCC VSS WP
Address Counter/ Register
Program Enable VPP EEPROM Array 4096 Bits (512 x 8)
High Voltage Generator and Program Timer
Decoder 1 of 512
Read/Write Amps
Data In/Out Register 8 Bits
Data Out Buffer
SO
Non-Volatile Status Register
SPITM is a trademark of Motorola Corporation. DS800002-1
© 1999 Fairchild Semiconductor Corporation NM25C041 Rev. C.1
1
www.fairchildsemi.com
NM25C041 4096-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
Connection Diagram
Dual-In-Line Package (N) and SO Package (M8) CS SO WP VSS 1 2 3 4 Top View 8 7 6 5 VCC HOLD SCK SI
DS800002-2
Pin Names
CS SO WP VSS SI SCK HOLD V CC Chip Select Input Serial Data Output Write Protect Ground Serial Data Input Serial Clock Input Suspends Serial Data Power Supply
Ordering Information NM 25 C XX LZ E XX
Package Temp. Range
Letter
N M8 None V E Blank L LZ 041 C Interface 25 NM
Description
8-pin DIP 8-pin SO 0 to 70°C -40 to +125°C -40 to +85°C 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V and <1µA Standby Current 4K, mode 1 CMOS SPI - 3 Wire Fairchild Non-Volatile Memory
Voltage Operating Range
Density
2
NM25C041 Rev. C.1
www.fairchildsemi.com
NM25C041 4096-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 sec.) ESD Rating -65°C to +150°C +6.5V to -0.3V +300°C 2000V
Operating Conditions
Ambient Operating Temperature NM25C041 NM25C041E NM25C041V Power Supply (VCC) NM25C041 0°C to +70°C -40°C to +85°C -40°C to +125°C 4.5V to 5.5V
DC and AC Electrical Characteristics 4.5V VCC 5.5V
Symbol
ICC ICCSB IIL IOL VIL V IH VOL VOH fOP tRI tFI tCLH tCLL tCSH tCSS tDIS tHDS tCSN tDIN tHDN tPD tDH tLZ tDF tHZ tWP
Parameter
Operating Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage SCK Frequency Input Rise Time Input Fall Time Clock High Time Clock Low Time Min CS High Time CS Setup Time Data Setup Time HOLD Setup Time CS Hold Time Data Hold Time HOLD Hold Time Output Delay Output Hold Time HOLD to Output Low Z Output Disable Time HOLD to Output High Z Write Cycle Time
Conditions
CS = VIL CS = VCC VIN = 0 to VCC VOUT = GND to VCC
Min
Max
3 50
Units
mA µA µA µA V V V V
-1 -1 -0.3 0.7 * VCC
1 1 VCC * 0.3 VCC + 0.3 0.4
IOL = 1.6 mA IOH = 0.8 mA VCC - 0.8
2.1 2.0 2.0 (Note 2) (Note 2) (Note 3) 190 190 240 240 100 90 240 100 90 CL = 200 pF 0 100 CL = 200 pF 240 100 14 Bytes 10 240
MHz µs µs ns ns ns ns ns ns ns ns ns ns ms ns ns ns ms
Capacitance (Note 4) TA = 25°C, f = 2.1/1 MHz
Symbol
COUT CIN
AC Test Conditions
Output Load Input Pulse Levels Timing Measurement Reference Level CL = 200 pF 0.1 * VCC - 0.9 * VCC 0.3 * VCC - 0.7 * VCC
Test
Output Capacitance Input Capacitance
Typ
3 2
Max
8 6
Units
pF pF
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: Minimum clock period is calculated by 1 divided by the maximum clock frequency Note 3: CS must be brought high for a minimum of tCSH between consecutive instruction cycles. Note 4: This parameter is periodically sampled and not 100% tested.
3
NM25C041 Rev. C.1
www.fairchildsemi.com
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