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Details, datasheet, quote on part number:P5Z22V10-DA
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Datasheet text preview:
INTEGRATED CIRCUITS
P5Z22V10 5V zero power, TotalCMOSTM, universal PLD device
Product specification Supersedes data of 1997 Apr 04 IC27 Data Handbook 1997 May 02
Philips Semiconductors
Philips Semiconductors
Product specification
5V zero power, TotalCMOSTM, universal PLD device
P5Z22V10
FEATURES
· Industry's first TotalCMOSTM 22V10 both CMOS design and
process technologies
· Fast Zero Power (FZPTM) design technique provides ultra-low
power and high speed Static current of less than 75µA Dynamic current 1/10 to 1/1000 that of competing devices Pin-to-pin delay of only 7.5ns
· Programmable output polarity · Synchronous preset/asynchronous reset capability · Security bit prevents unauthorized access · Electronic signature for identification · Design entry and verification using industry standard CAE tools · Reprogrammable using industry standard device programmers
DESCRIPTION
The P5Z22V10 is the first SPLD to combine high performance with low power, without the need for "turbo bits" or other power down schemes. To achieve this, Philips Semiconductors has used their FZPTM design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates. This results in the combination of low power and high speed that has previously been unattainable in the PLD arena. For 3V operation, Philips Semiconductors offers the P3Z22V10 that offers high speed and low power in a 3V implementation. The P5Z22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.
· True Zero Power device with no turbo bits or power down
schemes
· Function/JEDEC map compatible with
Bipolar UVCMOS EECMOS 22V10s
· Multiple packaging options featuring PCB-friendly flow-through
pinouts (SOL and TSSOP) 24-pin TSSOP--uses 93% less in-system space than a 28-pin PLCC 24-pin SOL 28-pin PLCC with standard JEDEC pin-out
· Available in commercial and industrial operating ranges · Advanced 0.5µ E2CMOS process · 1000 erase/program cycles guaranteed · 20 years data retention guaranteed · Varied product term distribution with up to 16 product terms per
output for complex functions
ORDERING INFORMATION
ORDER CODE P5Z22V10-7A P5Z22V10-7D P5Z22V10-7DH P5Z22V10DA P5Z22V10DD P5Z22V10DDH P5Z22V10IDA P5Z22V10IDD P5Z22V10IDDH PACKAGE 28-pin PLCC 24-pin SOL 24-pin TSSOP 28-pin PLCC 24-pin SOL 24-pin TSSOP 28-pin PLCC 24-pin SOL 24-pin TSSOP PROPAGATION DELAY 7.5ns 7.5ns 7.5ns 10ns 10ns 10ns 10ns 10ns 10ns TEMPERATURE RANGE 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C 40 to +85°C 40 to +85°C 40 to +85°C OPERATING RANGE VCC = 5.0V ±5% VCC = 5.0V ±5% VCC = 5.0V ±5% VCC = 5.0V ±5% VCC = 5.0V ±5% VCC = 5.0V ±5% VCC = 5.0V ±10% VCC = 5.0V ±10% VCC = 5.0V ±10% DRAWING NUMBER SOT261-3 SOT137-1 SOT355-1 SOT261-3 SOT137-1 SOT355-1 SOT261-3 SOT137-1 SOT355-1
1997 May 02
2
8531977 18019
Philips Semiconductors
Product specification
5V zero power, TotalCMOSTM, universal PLD device
P5Z22V10
PIN CONFIGURATIONS 28-Pin PLCC
IO/CLK VCC NC
PIN DESCRIPTIONS
PIN LABEL
F9 F8
DESCRIPTION Dedicated Input Not Connected Macrocell Input/Output Dedicated Input/Clock Input Supply Voltage Ground
I2
I1
I1 I11 NC
25 F7 24 F6 23 F5 22 NC 21 F4 20 F3 19 F2
4 I3 I4 I5 NC I6 I7 I8 5 6 7 8 9 10 11 12 I9
3
2
1
28
27
26
F0 F9 I0/CLK VCC GND
13 I10
14 GND
15 NC
16 I11
17 F0
18 F1
SP00474
24-Pin SOL and 24-Pin TSSOP
IO/CLK I1 I2 I3 I4 I5 I6 I7 I8 1 2 3 4 5 6 7 8 9 24 VCC 23 F9 22 F8 21 F7 20 F6 19 F5 18 F4 17 F3 16 F2 15 F1 14 F0 13 I11
I9 10 I10 11 GND 12
AP00475
1997 May 02
3
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