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Details, datasheet, quote on part number:PM7528FP
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Datasheet text preview:
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FEATURES On-Chip Latches for Both DACs +5 V to +15 V Operation DACs Matched to 1% Four Quadrant Multiplication TTL/CMOS Compatible Latch Free (Protection Schottkys not Required) APPLICATIONS Digital Control of: Gain/Attenuation Filter Parameters Stereo Audio Circuits X-Y Graphics
CMOS Dual 8-Bit Buffered Multiplying DAC AD7528
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
ORDERING GUIDE1 Model2 AD7528JN AD7528KN AD7528LN AD7528JP AD7528KP AD7528LP AD7528JR AD7528KR AD7528LR AD7528AQ AD7528BQ AD7528CQ AD7528SQ AD7528TQ AD7528UQ AD7528SE AD7528TE AD7528UE Temperature Range 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C Relative Gain Accuracy Error ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 4 LSB ± 2 LSB ± 1 LSB ± 4 LSB ± 2 LSB ± 1 LSB ± 4 LSB ± 2 LSB ± 1 LSB ± 4 LSB ± 2 LSB ± 1 LSB ± 4 LSB ± 2 LSB ± 1 LSB ± 4 LSB ± 2 LSB ± 1 LSB Package Option3 N-20 N-20 N-20 P-20A P-20A P-20A R-20 R-20 R-20 Q-20 Q-20 Q-20 Q-20 Q-20 Q-20 E-20A E-20A E-20A
The AD7528 is a monolithic dual 8-bit digital/analog converter featuring excellent DAC-to-DAC matching. It is available in skinny 0.3" wide 20-pin DIPs and in 20-terminal surface mount packages. Separate on-chip latches are provided for each DAC to allow easy microprocessor interface. Data is transferred into either of the two DAC data latches via a common 8-bit TTL/CMOS compatible input port. Control input DAC A/DAC B determines which DAC is to be loaded. The AD7528's load cycle is similar to the write cycle of a random access memory and the device is bus compatible with most 8-bit microprocessors, including 6800, 8080, 8085, Z80. The device operates from a +5 V to +15 V power supply, dissipating only 20 mW of power. Both DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor for each DAC.
PRODUCT HIGHLIGHTS
1. DAC to DAC matching: since both of the AD7528 DACs are fabricated at the same time on the same chip, precise matching and tracking between DAC A and DAC B is inherent. The AD7528's matched CMOS DACs make a whole new range of applications circuits possible, particularly in the audio, graphics and process control areas. 2. Small package size: combining the inputs to the on-chip DAC latches into a common data bus and adding a DAC A/DAC B select line has allowed the AD7528 to be packaged in either a small 20-pin DIP, SOIC, PLCC or LCCC. REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
NOTES 1 Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts will be marked with cerdip designator "Q." 2 Processing to MIL-STD-883C, Class B is available. To order, add suffix "/883B" to part number. For further information, see Analog Devices' 1990 Military Products Databook. 3 E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
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AD7528SPECIFICATIONS (V
Parameter STATIC PERFORMANCE 2 Resolution Relative Accuracy Version1 All J, A, S K, B, T L, C, U All J, A, S K, B, T L, C, U TA = +25°C 8 ±1 ± 1/2 ± 1/2 ±1 ±4 ±2 ±1 ± 0.007 ± 50 ± 50 8 15 ±1
REF
A = VREF B = +10 V; OUT A = OUT B = O V unless otherwise noted)
VDD = +15 V TA= +25°C TMIN, TMAX 8 ±1 ± 1/2 ± 1/2 ±1 ±4 ±2 ±1 ± 0.0035 ± 50 ± 50 8 15 ±1 8 ±1 ± 1/2 ± 1/2 ±1 ±5 ±3 ±1 ± 0.0035 ± 200 ± 200 8 15 ±1 Units Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max %/°C max nA max nA max k min k max % max DAC Latches Loaded with 00000000 Input Resistance TC = 300 ppm/°C, Typical Input Resistance is 11 k Test Conditions/Comments
VDD = +5 V TMIN, TMAX 8 ±1 ± 1/2 ± 1/2 ±1 ±6 ±4 ±3 ± 0.007 ± 400 ± 400 8 15 ±1
This is an Endpoint Linearity Specification
Differential Nonlinearity Gain Error
All Grades Guaranteed Monotonic Over Full Operating Temperature Range Measured Using Internal RFB A and RFB B Both DAC Latches Loaded with 11111111 Gain Error is Adjustable Using Circuits of Figures 4 and 5
Gain Temperature Coefficient 4 Gain/ Temperature Output Leakage Current OUT A (Pin 2) OUT B (Pin 20) Input Resistance (V REFA, VREFB) VREF A/VREF B Input Resistance Match DIGITAL INPUTS 3 Input High Voltage V IH Input Low Voltage V IL Input Current I IN Input Capacitance DB0DB7 WR, CS, DAC A/DAC B SWITCHING CHARACTERISTICS 4 Chip Select to Write Set Up Time t CS Chip Select to Write Hold Time t CH DAC Select to Write Set Up Time t AS DAC Select to Write Hold Time t AH Data Valid to Write Set Up Time t DS Data Valid to Write Hold Time t DH Write Pulse Width t WR POWER SUPPLY I DD
All All All All
All
All All All All All
2.4 0.8 ±1 10 15
2.4 0.8 ± 10 10 15
13.5 1.5 ±1 10 15
13.5 1.5 ± 10 10 15
V min V max µA max pF max pF max See Timing Diagram VIN = 0 or VDD
All All All All All All All All All
200 20 200 20 110 0 180 2 100
230 30 230 30 130 0 200 2 500
60 10 60 10 30 0 60 2 100
80 15 80 15 40 0 80 2 500
ns min ns min ns min ns min ns min ns min ns min mA max µA max See Figure 3 All Digital Inputs V IL or VIH All Digital Inputs 0 V or VDD
AC PERFORMANCE CHARACTERISTICS5
VDD = +5 V Parameter DC SUPPLY REJECTION (GAIN/VDD) CURRENT SETTLING TIME 2 Version1 TA = +25°C All All 0.02 350 0.04 400
(Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as Output Amplifiers)
VDD = +15 V Test Conditions/Comments To 1/2 LSB. Out A/Out B load = 100 . WR = CS = 0 V. DB0DB7 = 0 V to VDD or VDD to 0 V VREF A = VREF B = +10 V OUT A, OUT B Load = 100 CEXT = 13 pF WR = CS = 0 V DB0DB7 = 0 V to VDD or VDD to 0 V For Code Transition 00000000 to 11111111 DAC Latches Loaded with 00000000 DAC Latches Loaded with 11111111 0.01 180 0.02 200 % per % max VDD = ± 5% ns max
TMIN, TMAX TA= +25°C TMIN, TMAX Units
PROPAGATION DELAY (From Digital Input to 90% of Final Analog Output Current)
All
220
270
80
100
ns max
DIGITAL-TO-ANALOG GLITCH IMPULSE All OUTPUT CAPACITANCE C OUTA C OUTB C OUTA C OUTB AC FEEDTHROUGH 6 VREF A to OUT A VREF B to OUT B All
160 50 50 120 120 50 50 120 120
440 50 50 120 120 50 50 120 120
nV sec typ pF max pF max pF max pF max
All
70 70
65 65
70 70
65 65
dB max dB max
VREF A, VREF B = 20 V p-p Sine Wave @ 100 kHz
2
REV. A
AD7528
VDD = +5 V Parameter CHANNEL-TO-CHANNEL ISOLATION VREF A to OUT B VREFB to OUT A DIGITAL CROSSTALK HARMONIC DISTORTlON All All Version1 TA = +25°C All 77 77 30 85 VDD = +15 V Test Conditions/Comments Both DAC Latches Loaded with 11111111. VREF A = 20 V p-p Sine Wave @ 100 kHz VREF B = 0 V see Figure 6. VREF A = 20 V p-p Sine Wave @ 100 kHz VREF A = 0 V see Figure 6. Measured for Code Transition 00000000 to 11111111 VIN = 6 V rms @ 1 kHz TMIN, TMAX TA= +25°C TMIN, TMAX Units 77 77 60 85 dB typ dB typ nV sec typ dB typ
NOTES 1 Temperature Ranges are J, K, L Versions: 40°C to +85°C A, B, C Versions: 40°C to +85°C S, T, U Versions: 55°C to +125°C 2 Specifications applies to both DACs in AD7528. 3 Logic inputs are MOS Gates. Typical input current (+25°C) is less than 1 nA. 4 Guaranteed by design but not production tested. 5 These characteristics are for design guidance only and are not subject to test. 6 Feedthrough can be further reduced by connecting the metal lid on the ceramic package (suffix D) to DGND. Specifications subject to change without notice.
AD7528, ideal maximum output is VREF 1 LSB. Gain error of both DACs is adjustable to zero with external resistance.
Output Capacitance:
Capacitance from OUT A or OUT B to AGND.
Digital to Analog Glitch lmpulse:
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V Digital Input Voltage to DGND . . . . . . . 0.3 V, VDD + 0.3 V VPIN2, VPIN20 to AGND . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V VREF A, VREF B to AGND . . . . . . . . . . . . . . . . . . . . . . . ± 25 V VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C Operating Temperature Range Commercial (J, K, L) Grades . . . . . . . . . . . 40°C to +85°C Industrial (A, B, C) Grades . . . . . . . . . . . . 40°C to +85°C Extended (S, T, U) Grades . . . . . . . . . . . 55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
CAUTION:
The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal. Glitch impulse is measured with VREF A, VREF B = AGND.
Propagation Delay:
This is a measure of the internal delays of the circuit and is defined as the time from a digital input change to the analog output current reaching 90% of its final value.
Channel-to-Channel Isolation:
The proportion of input signal from one DAC's reference input which appears at the output of the other DAC, expressed as a ratio in dB.
Digital Crosstalk:
The glitch energy transferred to the output of one converter due to a change in digital input code to the other converter. Specified in nV secs.
PIN CONFIGURATIONS PLCC
1. ESD sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subjected to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. 2. Do not insert this device into powered sockets. Remove power before insertion or removal.
TERMINOLOGY Relative Accuracy: DIP, SOIC
Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full scale reading.
Differential Nonlinearity:
LCCC
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB max over the operating temperature range ensures monotonicity.
Gain Error:
Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For the REV. A 3
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