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Details, datasheet, quote on part number:PSMN035-150
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Datasheet text preview:
DISCRETE SEMICONDUCTORS
DATA SHEET
PSMN035-150B; PSMN035-150P N-channel TrenchMOS(TM) transistor
Product specification August 1999
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
FEATURES
· 'Trench' technology · Very low on-state resistance · Fast switching · Low thermal resistance
g
PSMN035-150B; PSMN035-150P
QUICK REFERENCE DATA
SYMBOL
d
VDSS = 150 V ID = 50 A RDS(ON) 35 m
s
GENERAL DESCRIPTION
SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:· d.c. to d.c. converters · switched mode power supplies The PSMN035-150P is supplied in the SOT78 (TO220AB) conventional leaded package. The PSMN035-150B is supplied in the SOT404 surface mounting package.
PINNING
PIN 1 2 3 tab gate drain1 source drain DESCRIPTION
SOT78 (TO220AB)
tab
SOT404 (D2PAK)
tab
2
1 23
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 °C to 175°C Tj = 25 °C to 175°C; RGS = 20 k Tmb = 25 °C Tmb = 100 °C Tmb = 25 °C Tmb = 25 °C MIN. - 55 MAX. 150 150 ± 20 50 36 200 250 175 UNIT V V V A A A W °C
1 It is not possible to make connection to pin:2 of the SOT404 package
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
AVALANCHE ENERGY LIMITING VALUES
PSMN035-150B; PSMN035-150P
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 47 A; tp = 100 µs; Tj prior to avalanche = 25°C; VDD 50 V; RGS = 50 ; VGS = 10 V; refer to fig;15 MIN. MAX. 460 UNIT mJ
IAS
-
50
A
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. SOT78 package, in free air SOT404 package, pcb mounted, minimum footprint 60 50 MAX. 0.6 UNIT K/W K/W K/W
ELECTRICAL CHARACTERISTICS
Tj= 25°C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55°C VDS = VGS; ID = 1 mA Tj = 175°C Tj = -55°C Drain-source on-state VGS = 10 V; ID = 25 A resistance Gate source leakage current VGS = ±10 V; VDS = 0 V Zero gate voltage drain VDS = 150 V; VGS = 0 V; current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance Tj = 175°C Tj = 175°C MIN. 150 133 2.0 1.0 TYP. MAX. UNIT 3.0 30 2 0.05 79 17 33 25 138 79 93 3.5 4.5 7.5 4720 456 208 4.0 6 35 98 100 10 500 V V V V V m m nA µA µA nC nC nC ns ns ns ns nH nH nH pF pF pF
ID = 50 A; VDD = 120 V; VGS = 10 V
VDD = 75 V; RD = 1.5 ; VGS = 10 V; RG = 5.6 Resistive load Measured from tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
August 1999
3
Rev 1.000
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