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Details, datasheet, quote on part number:PZ5032-CS7A44
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Datasheet text preview:
INTEGRATED CIRCUITS
Xilinx has acquired the entire Philips CoolRunner Low Power CPLD Product Family. For more technical or sales information, please see: www.xilinx.com
XCR5032C 32 macrocell CPLD with enhanced clocking
Product specification Supersedes data of 1998 Jun 24 IC27 Data Handbook 1998 Jul 23
Philips Semiconductors
Philips Semiconductors
Product specification
32 macrocell CPLD with enhanced clocking
XCR5032C
Xilinx has acquired the entire Philips CoolRunner Low Power CPLD Product Family. For more technical or sales information, please see: www.xilinx.com FEATURES DESCRIPTION
· Industry's first TotalCMOSTM PLD both CMOS design and
process technologies power and very high speed
· Fast Zero Power (FZPTM) design technique provides ultra-low · High speed pin-to-pin delays of 6ns · Ultra-low static power of less than 75µA · Dynamic power that is 70% lower at 50MHz than competing · 100% routable with 100% utilization while all pins and all · Deterministic timing model that is extremely simple to use · Up to 6 clocks with programmable polarity at every macrocell · 5 Volt, In-System Programmable (ISP) using a JTAG interface
On-chip supervoltage generation ISP commands include: Enable, Erase, Program, Verify Supported by multiple ISP programming platforms 4 pin JTAG interface (TCK, TMS, TDI, TDO) JTAG commands include: Bypass, Idcode macrocells are fixed devices
The PZ5032C CPLD (Complex Programmable Logic Device) is a member of the Fast Zero Power (FZPTM) family of CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZPTM design technique, the PZ5032C offers true pin-to-pin speeds of 6ns, while simultaneously delivering power that is less than 75µA at standby without the need for `turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD--70% lower at 50MHz. These devices are the first TotalCMOSTM PLDs, as they use both a CMOS process technology and the patented full CMOS FZPTM design technique. For 3V applications, Philips also offers the high speed PZ3032C CPLD that offers pin-to-pin speeds of 8ns. The Philips FZPTM CPLDs introduce the new patent-pending XPLATM (extended Programmable Logic Array) architecture. The XPLATM architecture combines the best features of both PLA and PALTM type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLATM structure in each logic block provides a fast 6ns PALTM path with 5 dedicated product terms per output. This PALTM path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 8ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. The PZ5032C CPLDs are supported by industry standard CAE tools (Cadence, Exemplar Logic, Minc, Mentor, Synopsys, Synario, Viewlogic, OrCAD), using text (Abel, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses either Minc or Philips Semiconductors-developed tools. The PZ5032C CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. The PZ5032C also includes an industry-standard, IEEE 1149.1, JTAG interface through which In-System Programming (ISP) and reprogramming of the device are supported.
· Support for complex asynchronous clocking · Innovative XPLATM architecture combines high speed with · 1000 erase/program cycles guaranteed · 20 years data retention guaranteed · Logic expandable to 37 product terms · PCI compliant · Advanced 0.5µ E2CMOS process · Security bit prevents unauthorized access · Design entry and verification using industry standard and Philips · Reprogrammable using industry standard device programmers · Innovative Control Term structure provides either sum terms or
product terms in each logic block for: Programmable 3-State buffer Asynchronous macrocell register preset/reset Up to 2 asynchronous clocks CAE tools extreme flexibility
· Programmable global 3-State pin facilitates `bed of nails' testing · Available in both PLCC and TQFP packages
Table 1. PZ5032C Features
PZ5032C Usable gates Maximum inputs Maximum I/Os Number of macrocells I/O macrocells Buried macrocells Propagation delay (ns) Packages 1000 36 32 32 32 0 6.0 44-pin PLCC, 44-pin TQFP without using logic resources
PAL is a registered trademark of Advanced Micro Devices, Inc.
1998 Jul 23
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8532080 19774
Philips Semiconductors
Product specification
32 macrocell CPLD with enhanced clocking
PZ5032C
ORDERING INFORMATION
ORDER CODE PZ5032CS6A44 PZ5032CS7A44 PZ5032CS10A44 PZ5032CS6BC PZ5032CS7BC PZ5032CS10BC DESCRIPTION 44-pin PLCC, 6ns tPD 44-pin PLCC, 7.5ns tPD 44-pin PLCC, 10ns tPD 44-pin TQFP, 6ns tPD, 44-pin TQFP, 7.5ns tPD 44-pin TQFP, 10ns tPD DESCRIPTION Commercial temp range, 5 volt power supply, ± 5% Commercial temp range, 5 volt power supply, ± 5% Commercial temp range, 5 volt power supply, ± 5% Commercial temp range, 5 volt power supply, ± 5% Commercial temp range, 5 volt power supply, ± 5% Commercial temp range, 5 volt power supply, ± 5% DRAWING NUMBER SOT187-2 SOT187-2 SOT187-2 SOT376-1 SOT376-1 SOT376-1
XPLATM ARCHITECTURE
Figure 1 shows a high level block diagram of a 32 macrocell device implementing the XPLATM architecture. The XPLATM architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins. From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunnerTM family unique is what is inside each logic block and the design technique used to implement these logic blocks. The contents of the logic block will be described next.
PRODUCT terms, and are used to control the preset/reset and output enables of the 16 macrocells' flip-flops. In addition, two of the control terms can be used as clock signals (see Macrocell Architecture section for details). The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density. Each macrocell has 5 dedicated product terms from the PAL array. The pin-to-pin tPD of the PZ5032C device through the PAL array is 6ns. This performance is equivalent to the fastest 5 volt CPLD available today. If a macrocell needs more than 5 product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32 product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using 1 or all 32 PLA product terms is just 2ns. So the total pin-to-pin tPD for the PZ5032C using 6 to 37 product terms is 8ns (6ns for the PAL + 2ns for the PLA).
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. The 6 control terms can individually be configured as either SUM or
MC0 MC1 I/O MC15 16 16 LOGIC BLOCK 36 ZIA 16 16 36 LOGIC BLOCK
MC0 MC1 I/O MC15
SP00550
Figure 1. Philips XPLA CPLD Architecture
1998 Jul 23
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