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Details, datasheet, quote on part number:SAA2023GP
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
SAA2023 Drive processor for DCC systems
Preliminary specification File under Integrated Circuits, IC01 May 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
FEATURES · Operating supply voltage: 4.5 to 5.5 V · Low power dissipation: 260 mW at 5.0 V · Single chip digital equalizer, tape formatting and error correction · 8-bit flash analog-to-digital converter (ADC) for low symbol error rate · Two switchable Infinite Impulse-Response (IIR) filter sections · 10-tap Finite Impulse-Response (FIR) filter per main data channel, with 8 bit coefficients, identical for all main channels · 10-tap FIR filter for the AUX channel · Analog and digital eye outputs · Interrupt line triggered by internal auxiliary envelope processing e.g. label, counter, and others · Robust programmable digital PLL clock extraction unit · Low power SLEEP mode · Slew rate limited Electromagnetic Compatibility (EMC) friendly output · Digital Compact Cassette (DCC) optimized error correction · Programmable symbol synchronization strategy for tape input data · Microcontroller control of capstan servo possible during playback and recording ORDERING INFORMATION PACKAGE TYPE NUMBER PINS SAA2023H SAA2023GP Note 80 80 PIN POSITION TQFP80(1) QFP80(1) MATERIAL plastic plastic
SAA2023
· Frequency and phase regulation of capstan servo during playback · Choice of Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) types for system Random Access Memory (RAM) · Scratch pad RAM for microcontroller in system RAM · Integrated interface for Precision Adaptive Sub-band Coding (PASC) data bus · Three wire microcontroller `L3' interface · Protection against invalid auxiliary data · Seamless joins between recordings. GENERAL DESCRIPTION The SAA2023 performs the drive processor function in the DCC system. This function is built up of digital equalizer, error correction and tape formatting functions. The digital equalizer is intended for use with DCC read amplifiers TDA1318 or TDA1380. The tape formatting and error correction circuit is intended for use with PASC ICs SAA2003 and SAA2013, and write amplifiers TDA1319 or TDA1381.
CODE SOT315-1 SOT318-2
1. When using reflow soldering it is recommended that the Dry Packing instructions in the "Quality Reference Pocketbook" are followed. The pocketbook can be ordered using the code 9398 510 34011.
May 1994
2
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
BLOCK DIAGRAM
SAA2023
handbook, full pagewidth
SAA2023
DIGITALTO-ANALOG CONVERTER
ANAEYE RDSYNC RDMUX BIAS Vref(p) Vref(n)
PHASE LOCKED LOOP
ZERO CROSSING
FIR (1)
IIR (2)
ANALOG TO-DIGITAL CONVERTER
TAPE INPUT BUFFER SBDIR SBMCLK SBEF SBDA SBCL SBWS
AUXILIARY ENVELOPE DETECTION
EQUALIZER MODULE
SUB-BAND I 2S INTERFACE
INTERNAL DATA BUS
TAPE OUTPUT BUFFER
TCLOCK WDATA
ERROR CORRECTOR
RAM INTERFACE
CONTROL INTERFACE
SPEED URDA RESET SLEEP L3REF L3DATA
8 11
6
MGB378
A11 to A16
L3MODE
PINO1
PINO2
OEN
D0 to D7
L3INT
WEN
A0 to A10
(1) FIR = Finite Impulse-Response. (2) IIR = Infinite Impulse-Response.
Fig.1 Block diagram.
May 1994
3
L3CLK
PINI
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