Details, datasheet, quote on part number: STLC
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Features, Applications

2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE

GENERAL FEATURES SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS MEETS OR EXCEEDS ETSI EUROPEAN STANDARD SINGLE 5V SUPPLY DIP28 AND PLCC44 PACKAGE HCMOS3A SGS-THOMSON ADVANCED 1.2µm DOUBLE-METAL CMOS PROCESS ROUND TRIP DELAY MEASUREMENT EXTENDED TEMPERATURE RANGE TO +70°C)

TRANSMISSION FEATURES 160 KBIT/S FULL DUPLEX TRANSCEIVER 2B1Q LINE CODING WITH SCRAMBLER/DESCRAMBLER SUPPORTS BRIDGE TAPS, SPLICES AND MIXED GAUGES >70DB ADAPTIVE ECHO-CANCELLATION ON CHIP HYBRID CIRCUIT DECISION FEEDBACK EQUALIZATION ON CHIP ANALOG VCO SYSTEM DIRECT CONNECTION TO SMALL LINE TRANSFORMER

SYSTEM FEATURES ACTIVATION/DEACTIVATION CONTROLLER ON CHIP CRC CALCULATION AND VERIFICATION INCLUDING TWO PROGRAMMABLE BLOCK ERROR COUNTERS EOC CHANNEL AND OVERHEAD-BITS TRANSMISSION WITH AUTOMATIC MESSAGE CHECKING GCI AND µW/DSI MODULE INTERFACES COMPATIBLE DIGITAL LOOPBACKS COMPLETE (2B+D) ANALOG LOOPBACK IN LT ELASTIC DATA BUFFERS AND BACKPLANE CLOCK DE-JITTERIZER AUTOMODE NT1 AND REPEATER "U ACTIVATION ONLY" IN NT1

IDENTIFICATION CODE AS PER GCI STANDARD DECT FRAME SYNCHRONIZATION EASILY INTERFACEABLE WITH ST5451 (HDLC & GCI CONTROLLER), / STLC5465 AND ANY OTHER GCI, IDL or TDM COMPATIBLE DEVICES

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

INDEX DISTINCTIVE CHARACTERISTICS. Page GENERAL DESCRIPTION. PIN FUNCTION. FUNCTIONAL DESCRIPTION. Digital Interfaces. µW/DSI mode. µW Control Interface. Write Cycle. Read Cycle. Digital System Interface. GCI mode. Frame structure. Physical links. Monitor channel. C/I channel. Line coding and frame format. Transmit section. Receive section. Elastic buffers. Dect synchronization. M channel. EOC. M4 channel. Spare M5 and M6 bits. CRC calculation checking. Loopbacks.

Identification code. 34 General purpose I/Os. 34 Test functions. 35 Turning on and off the device. Power on initialization. Line signal detection. Power up control. Power down control. Power up state. Power down state. Activation deactivation sequencing. Case of restricted activation. Reset of activation / deactivation state machine. Hardware reset. Quiet mode. Automode.

Command/Indication (C/I) codes. 37 Internal register description. 41 Line interface circuit. Board layout. 55

APPENDIX A: STATE MATRIX. 60 APPENDIX B: ELECTRICAL PARAMETERS. 62

 

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