|Datasheet||Download STLC5432 datasheet
ONE CHIP SOLUTION FROM PCM BUS TO TRANSFORMER (CEPT STANDARD) ISDN PRIMARY ACCESS CONTROLLER (COMPATIBLE WITH ETSI, OPTION 1 AND 2) HDB3/BIN ENCODER AND DECODER ON CHIP MULTIFRAME STRUCTURE HANDLING BUILT IN CRC4 EASY LINK TO ST5451/MK50H25/MK5027 LINK CONTROLLERS. DATA RATE: 2048, 4096 AND 8192 Kb/s FOR MULTIPLEXED APPLICATIONS FOUR LOOPBACK MODES FOR TESTING PSEUDO RANDOM SEQUENCE GENERATOR AND ANALYZER FOR ON-LINE, OFFLINE AND AUTOTEST CLOCK RECOVERY CIRCUITRY ON CHIP 64 BYTE ELASTIC MEMORY FOR TIME COMPENSATION AND AUTOMATIC FRAME AND SUPERFRAME ALIGNMENT 32 ON CHIP REGISTERS FOR CONFIGURATIONS, TESTING, ALARMS, FAULT AND ERROR RATE CONTROL. AUTO ADAPTATIVE DETECTION THRESHOLD AUTOMATIC EQUALIZER OPTION 5V POWER SUPPLY AMI OR HDB3 CODE SELECTION PARALLEL OR SERIAL MICROPROCESSOR INTERFACE OPTION BOTH µp AND STAND ALONE MODE AVAILABLE DESCRIPTION STLC5432, CMOS device, interfaces the multiplex system to the physical CEPT Transmission link at 2048Kb/s. Furthermore, thanks to its flexibility, it is the optimum solution also for the ISDN application as PRIMARY RATE CONTROLLER. The receive circuit performances exceed CCITT recommendation and the line driver outputs meet the G.703 specifications. STLC5432 is the real single chip solution that allows the best system flexibility and easy design. STLC5432 can work either or 8192 Kbit/s systems programming the CR4 register (when parallel micro interface selected).
Name VCCD1 VCCD2 VCCA GNDD GNDA L02 XTAL1 Pin Type Function Positive power supply inputs for the digital (VCCD1) and analog (VCCA) sections and for microprocessor interface signals (VCCD2). They must be +5 Volts and must be directly connected together. Negative power supply pins which must be connected together close to the device. All digital and analog signals are referred to these pins, which are normally at the system ground. Receive HDB3 signal differential inputs from the line transformer. Positive power supply output for fixing reference voltage to the receive transformer. Typical value is 2.375V Transmit HDB3 signal differential outputs to the line transformer.When used with an appropriate transformer, the line signal conforms to the output specifications in CCITT with a nominal pulse amplitude of 3 volts for a 120 load on line side. The master clock input which requires either a parallel resonance crystal to be tied between this pin and or a clock input from a stable source. This clock does not need to be synchronized to the system clock. Crystal specifications = 32764 kHz ± 50 ppm parallel resonant; RS 20 loaded with 33pF to GND each side. The output of the crystal oscillator, which should be connected to one end of the crystal if used. High clock received, bit clock. When the device has recovered the clock from the HDB3 signal, HCR signal is synchronized to the remote circuit. The HCR frequency is either if 8MCR bit of CR1 Register is put or 4096 kHz 8MCR is set to 0. Low clock received, frame clock. When the device has recovered the clock from the HDB3 signal, LCR signal is synchronized to the remote entity. The LCR frequency is 8 kHz if 8KCR bit is set or 4 kHz if 8KCR bit is set to 0. When the remote clock is not recovered, HCR and LCR frequency are synchronized to master clock (16384 kHz). HCR and LCR can be used by the system in Terminal Mode.These two clocks can be used by the transmit function of the device. Binary Receive Data Output, 2048 kbit/s or 64kbit/s. Receive Clock output, 2048 kHz or 64kHz. After decoding, Binary Data and clock associated are provided for different applications. Binary Receive Data Input. 2048 kbit/s. Receive Clock Input 2048 kHz. Binary Transmit Data Output, 2048 kbit/s or output clock at 64kHz. Before encoding Binary Data is provided to different applications (Optical Interface for instance). Local clock is associated to this data. This binary signal can replace BXD internal signal to be encoded if SELEX bit (CR1 Register) is set to 1. Data Output. 30 B+D primary access data received from the line.Data can be shifted out from the tristate output DOUT at the LCLK frequency on the rising edges during all the time slots,except Time Slot Zero in accordance with TSOE bit : If parallel micro-interface is selected, DOUT is at high impedance after Reset. DOUT is at low impedance after writing CR4 register. Data Input : 30B+D primary access data to transmit to the line.Data can be shifted in at the LCLK frequency on the falling edges during all the time slots, except Time Slot Zero, in accordance with TSOE bit (CR1 Register).
Name LCLK Pin 23 Type I Function Local Clock : this clock input determines the data shift rate on the two digital multiplexes. This clock frequency can be indifferently or 16384kHz. Data Out and Data In rate is always 2048 kbit/s when Serial Interface microprocessor: an internal automatic mechanism divides by two the frequency if 4096 kHz. Local Frame Synchronization for the Receiver. This clock input defines the start of the frame on the digital multiplex Data (pin DOUT). This clock frequency can be indifferently 8 kHz or a submultiple of 8 kHz. Local Frame Synchronization for the Transmitter. This clock input defines the start of the frame on the digital multiplex Data (pin DIN). This clock frequency can be indifferently 8 kHz or a submultiple of 8 kHz. If submultiple of 8 kHz, LFSX defines the start of even frame on DIN. The TSO of this even frame will contain the Frame Alignment Signal (FAS) on the line. Alarm 0 Output, alarm 1 Output. These pins are open drain outputs which are normally in high impedance state. Z 0Volt Alarm definitions Frame or Multiframe recovered, A bit received is 0. Frame or Multiframe recovered, A bit received is 1 Frame and Multiframe lost, AIS Alarm Indication Signal is detected. Frame and Multiframe lost, AIS Alarm Indication Signal is not detected.
DPI input: The internal DPLL is synchronized either by the signal applied on DPI input (if DPIS bit of CR5 register or by the 2MHz clock recovered from the line. Stand Alone : When this pin is connected to 5 Volts, the device works without microprocessor. The configuration is given by the values per default of programmable registers. BRDI and BXDI must not be used. RESET: When this pin is put to 5 Volts during ns at least every programmable register is reset (value per default). When this pin is set at zero Volt, the type of microprocessor is selected P0, P1 pins.
Processor interface. These two input pins define the microprocessor interface chosen. P1 P0 Microprocessor Interface ----------------------------------------------------------------------------------0 0 Serial Microprocessor Interface 1 ST9 Microprocessor Interface 1 0 Multiplexed Motorola processor interface 1 Multiplexed Intel processor interface Address Strobe/Address Latch Enable. Input Chip Select. A high level on this input selects the PRCD for a read write operation. Read/Write/Write Data. Input. Data Strobe/Read Data. Input. Address/Data to 7. Input-Output. Interrupt Request. The signal is activated low when the PRCD requests an interrupt. is an open drain output.
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