Details, datasheet, quote on part number: STLC5460
PartSTLC5460
Category
Description
CompanyN.A.
DatasheetDownload STLC5460 datasheet
  

 

Features, Applications

BOARD CONTROLLER FOR TO 16 ISDN LINES OR 16 VOICE SUBSCRIBERS. TWO SERIAL INTERFACES : -PCM Four bidirectional multiplexes -GCI One (or two) at 2 Mb/s. NON BLOCKING SWITCH FOR 128 CHANNELS OR 64 KB/S BANDWIDTH). N CONSECUTIVE 64 kb/s CHANNELS FROM AN INPUT MULTIPLEX CAN BE SWITCHED AS A SINGLE X 64 kbit/s CHANNEL TO AN OUTPUT MULTIPLEX AT 2048 kb/s. TIME SLOT ASSIGNMENT FREELY PROGRAMMABLE FOR EVERY CONNECTED SUBSCRIBER. PROGRAMMABLE PCM DATA RATES TO 8192 kb/s.CONSTANT DATA RATE AT 2 Mb/s ON GCI SIDE. PCM interface : - Simple and double clock frequency selectable;. - Programmable clock shift - Tristate mode control signals for external drivers. GCI interface : - Six bits or four bits Command/indicate channel selectable for analog or digital equipment PIN CONNECTION (Top view)

- Command/IndicateMonitor channels validated or not Microprocessor access to two selected bidirectional channels of GCI and/or PCM. Multicontrollers for layer 1 functions : - C/I protocol controller for to 16 C/I channels - Monitor protocol controller for to 16 Monitor channels. Standard microprocessor interface with multiplexed address/data bus or separate address data buses. PLCC44 pins PACKAGE

DESCRIPTION The Line Card Interface Controller, is a monolithic switching device for the path control to 128 channels 32, 64 kbps bandwidth. Two consecutive 64 kbps channels may also be handled as a quasi single 128 kbps channel. For these channels, the LCIC performs nonblocking space time switching between two serial interfaces: the system interface (or PCM interface) and the general component interface (GCI). PCM interface can be programmed to operate at different data rates between 2048 and 8192 kbps. The PCM interface consists up to four duplex ports with a tristate indication signal for each output line. The GCI interface can be selected to be PCM interface at 2Mbit/s. The LCIC can be programmed to communicate with GCI compatible devices such as STLC3040 (SLIC), STLC5411 (U interface) and others. The device manages the layer 1 protocol buffering the Command/Indicate and Monitor channels for GCI compatible devices. Due to its capability to switch channels of different BLOCK DIAGRAM bandwidths, the STLC5460 can handle to 16 ISDN subscribers with their 2B+D channel structure in GCI configuration, to 16 analog subscribers. Since its interfaces can operate at different data rates, the LCIC is an ideal device for data rate adaptation between PCM interface to 8Mb/s and GCI at 2Mb/s. The device gives the possibility of checking the correct communication inside the PBX or Public Central Office providing : - independentPCM delay setting - PCM comparison function - Pseudo RandomSequenceGeneratorandAnalyser. Moreover, the LCIC is one of the key building blocks for networks with either central, distributed or mixed signaling and packet data handling architectures associated with ST5451 (HDLC controller). The device is controlled by a standard 8 bit parallel microprocessor interface with a multiplexed address-data bus. The device may optionally be controlled by separate address and data buses.

COMMAND MEMORY 194 WORDS OF 14 BITS COUNTERS 6 bits COUNTERS
1 bit for 16 tristate 4 PCM PARALLEL SERIAL SHIFTING 2 GCI SPECIAL SWITCH 32, 64 KB/S

Symbol VDD1 A0 Pin number 1 2 Type I Supply Voltage 5V, 5%. Non Multiplexed Mode: this input interfaces to the system's address bus to select an internal register for a read or write access. Multiplexed Mode: A0 at VDD, NRDY/NWAIT pin delivers NWAIT A0 at VSS, NRDY/NWAIT pin delivers NREADY Receive PCM interface Data : Serial data is received at these lines at standard TTL or CMOS levels. Function

Non Multiplexed Mode: this input interfaces to the system's address bus to select an internal register for a read or write access. Multiplexed Mode: A1 at VDD, NCS signal provided by the system is not inverted by the circuit. A1 at VSS, NCS signal provided by the system is inverted by the circuit. Tristate control for the PCM interface. These lines are low when the corresponding TxD outputs are valid.

Transmit PCM interface Data : Serial data is sent by these lines at standard TTL or CMOS levels. These pins can be tristated.

PCM interface frame synchronization pulse. PCM interface data clock, single or double rate. Non Multiplexed Mode: this input interfaces to the system's address bus to select an intenal register for a read or write access. Multiplexed Mode: A2 at VDD, AS/ALE signal providedby the system is not inverted by the circuit A2 at VSS, AS/ALE signal provided by the system is inverted by the circuit Address Data Bus. If the multiplexed address/data P interface bus mode is selected these pins transfer data and commands between the P and the If a demultiplexed mode is used, these bits interface with the system data bus.

Ground : 0V Motorola like mode: Data Strobe Intel Like Mode: Not Read The signal indicates a read operation, active low Motorola like mode: Read/Write Intel Like Mode: Not Write The signal indicates a Write operation, active low. Not Chip select. A low on this line selects the STLC5460 for a read/write operation.

(I) Input (O) Output (IO) In/Output (OD) Open Drain

 

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