Details, datasheet, quote on part number: STLC7545
PartSTLC7545
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CompanyN.A.
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Features, Applications

FULL ECHO CANCELLING CAPABILITY FULLY COMPATIBLE WITH THE ST7544 16-BIT OVERSAMPLING A/D AND D/A CONVERTERS - Programmable down-sampling frequency from 22kHz. - Sampling frequency can be x symbol rate. - ProgrammableOversampling 192 x sampling frequency). - The STLC7545 can work with external oversampling clocks. - Programmable symbol rate and 3491). - Bit rates 600bps, 1200 and all multiples to 38400bps can be generated. - Dynamic range : 92dB with a sampling frequency 9600Hz, oversampling ratio 160. - Total harmonic distortion -89dB. ON CHIP REFERENCE VOLTAGE THREE PROGRAMMABLE DIGITAL FILTERS SECTIONS (up to 14th order each, coefficients loaded into RAM) - Tx interpolation filter - Rx decimation filter - Rx reconstruction filter ANCILLARY CONVERTERS FOR EYE-DIAGRAM MONITORING CLOCK SYSTEM BASED ON DIGITAL PHASE LOCKED LOOPS - Separate Tx DPLL and Rx DPLL - Terminal clock input for Tx synchronizationon all multiples of 2400Hz (VFast synchronization mode) or on sub-multiple of baud rate (7544 synchronization mode) - Bit, Baud, sampling and highest synchronous clock outputs - Maximum master clock frequency is 38MHz SINGLE OR DUAL SYNCHRONOUS SERIAL INTERFACE TO DSP ANALOG POWER SUPPLY VOLTAGE : +5V DIGITAL POWER SUPPLY FROM TO 5V LOW POWER CONSUMPTION - 100mW operating power at the nominal crystal frequencyof 3.3V) - Less than 5mW in the Low-Power Reset Mode 0.7m CMOS PROCESS TQFP44 (1.4mm body thickness)

PLCC44 (Plastic Leaded Chip Carrier) ORDER CODE : STLC7545CFN
x 1.4mm) (Thin Full Plastic Quad Flat Pack) ORDER CODE : STLC7545TQFP4Y

DESCRIPTION TheSTLC7545is a single chipAnalogFront-End(AFE) designed to implement high speed voice-grade Modems to 384kbpswith echo cancelling capability. Associated with one or several Digital Signal Processors (DSP), it provides a powerful solution for the implementation of multi-mode Modems meeting CCITT V.22, V.22 bis, It is fully compatiblewith theST7544and is also well suited emerging applications involving bit rates to 38400bps (in the VFast synchronizationmode). The transmit section includes a 16-bit over-sampling D/A converter with a programmable interpolating filter. Thereceive section includesa 16-bit oversamplingA/D converter with two programmable filters (one for decimation andtheotherforreconstruction).Oversampling ratio is selectable to either or 192. Two on a scopeformodem performanceadjustment. Two independantclock generator systems are provided, one synchronized on the Tx rate and the other on the Rx rate. In External Clock Mode, external oversampling clocks can be provided to the chip. Two independant synchronous serial interfaces (SSI) allow several versatile ways of communicating with standard DSPs. To save power, e.g. in lap-top modem applications, the lowpower reset mode can be used to reduce the power consumption to less than 5mW.

I.3 II III IV.6 IV.7 PIN DESCRIPTION. PIN CONNECTIONS (Top View). PIN LIST. PIN FUNCTION. BLOCK DIAGRAM. FUNCTIONAL DESCRIPTION. SIGNAL TRANSFER BLOCK DIAGRAM. TRANSMIT D/A SECTION. Interpolation Filters. Programmable Interpolation Filter (IIR1). FIR Filter (FIR1). D/A Converter. Receive A/D Section. A/D Converter. Decimation Filters. FIR Filter (FIR2). Programmable Decimation Filter (IIR2). Eye-diagram Display. RECEIVE RECONSTRUCTION SECTION. Programmable Interpolation Filter (IIR3). FIR Filter (FIR3). CLOCK GENERATION. Transmit DPLL. Transmit Clocks. Internal Mode. External Mode. Receive DPLL. Receive Clocks. Internal Mode. External Mode. SERIAL INPUT/OUTPUT SYNCHRONOUS INTERFACES. Tx Clock Related Registers. Rx Clock Related Registers. SERIAL INTERFACE OPERATION. DUAL SERIAL INTERFACE MODE (SSIA, SSIB). SINGLE SERIAL INTERFACE MODE. COEFFICIENT LOADING MODE. COEFFICIENT READING. CRYSTAL SELECTION (XTAL10, XTAL11). FRAME FREQUENCY PROGRAMMING. INITIALIZATION and LOW-POWER RESET MODE.

VI.2.13 VI.2.14 CIRCUIT PROGRAMMING. MODE FIELD. ADDRESS FIELD. RAM Address Field. Transmit Control Register Address Field. Receive Control Register Address Field. CONTROL REGISTER DATA FIELD. Transmit Control Register Programming. Receive Control Register Programming. Control Bit Function Summary. TxCTRL Word. RxCTRL Word. PROGRAMMABLE FUNCTIONS. TRANSMIT SECTION. Transmit Bit Rate Clock Frequency Programming with FQ=36.864MHz. Transmit Bit Rate Clock Frequency Programming with FQ=25.8048MHz. Transmit Bit Rate Clock Frequency Programming with FQ=18.432MHz. Transmit Bit Clock Frequency Programming. Divisor Rank. Transmit Sampling Clock Frequency Programming with FQ=36.864MHz. Transmit Sampling Clock Frequency Programming with FQ=25.8048MHz. Transmit Sampling Clock Frequency Programming with FQ=18.432MHz. Transmit Sampling Clock Frequency Programming. Divisor Rank. Transmit Baud Rate Frequency Programming. Divisor Rank. Highest Synchronous Transmit Frequency Programming. Divisor Rank. Band Split Mode. Transmit Synchronization Signal Programming. Clock Mode Programming & R2 Divisor. Transmit Attenuator Programming. Phase Comparator Frequency and Decimation or Interpolation Ratio. Phase Shift Frequency. Transmit Test Programming. RECEIVE SECTION. Receive Bit Rate Clock Frequency Programming with FQ=36.864MHz. Receive Bit Rate Clock Frequency Programming with FQ=25.8048MHz. Receive Bit Rate Clock Frequency Programming with FQ=18.432MHz. Receive Bit Rate Clock Frequency Programming. Divisor Rank. Receive Sampling Clock Frequency Programming with FQ=36.864MHz. Receive Sampling Clock Frequency Programming with FQ=25.8048MHz. Receive Sampling Clock Frequency Programming with FQ=18.432MHz. Receive Sampling Clock Frequency Programming. Divisor Rank. Receive Baud Rate Frequency Programming. Divisor Rank. Highest Synchronous Transmit Bit Frequency Programming. Divisor Rank. Receive Fine Phase Shift Programming. Receive Coarse Phase Shift Programming. Interpolation Ratio. Receive Test Programming & R2 Divisor.


 

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