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Details, datasheet, quote on part number:UPD70116
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Datasheet text preview:
********** C-MOS 8-BIT MICROPROCESSOR
--TOP VIEW-- 47 HLDRQ (RQ/AK0) IN/OUT 45 HLDAK (RQ/AK1) IN/OUT
I UPD70108HGC(1/3) L08
44 WR (BUSLOCK) OUT
42 BUF R/W (BS1) OUT
50 LBS0 (HIGH) OUT *
NC 52
NC 46
41 BUFEN (BS0) OUT
43 IO/M (BS2) OUT
51 A19/PS3 OUT
48 RD OUT
49 S/LG IN
A18/PS2 1 O
UT
NC 40 39 ASTB (QS0)
OUT
A17/PS1 2 O
UT
38 INTAK (QS1)
OUT
A16/PS0 3 O
UT
37 POLL IN 36 READY IN 35 RESET IN GND 34 GND 33 NC 32 GND 31 30 CLK IN 29 INT IN 28 NMI IN NC 27 14 NC A10 OUT 15 A9 OUT 16 A8 OUT 17 AD7 IN/OUT 18 AD6 IN/OUT 19 AD5 IN/OUT 20 AD4 IN/OUT 21 AD3 IN/OUT 22 AD2 IN/OUT 23 AD1 IN/OUT 24 AD0 IN/OUT 25 26 NC
A15 OUT 4 5 VDD(+5 or +3V) 6 VDD(+5 or +3V) 7 GND 8 GND IC 9 A14 OUT 10 A13 OUT 11 A12 OUT 12 A11 OUT 13
TYPE PD70108, 70116 UPD70108H, 70116H
U
V +DD 5V +5 or +3V
*
UPD70108, 70108H ; LBS0 (HIGH) OUT UPD70116, 70116H ; UBE OUT
UPD70108HGC(2/3) NIN P O. 38 4 39 41 42 43 44 45 57 0 FUNCTION S/LG=HIGH LEVEL S/LG=LOW LEVEL QS1 IA TAK N B STB B S0 B UFEN BS0 UF R/W I BS1 W/M O B S2 HR R SLOCK U H LDAK RQ/AK1 L LDRQ H Q/AK0 BS0 (UPD70108/H) IGH LEVEL
C INPUT HLK I LDRQ NT N P MI ROLL READY S ESET O/LG A UTPUT 16/PS0 - A19/PS3 B ASTB S0 - BS2 BUFEN B BUF R/W HUSLOCK I LDAK
; ; ; ; ; ; ; ; ; CLOCK HOLD REQUEST MASKABLE INTERRUPT NON-MASKABLE INTERRUPT POLL CHECK READ/WRITE CYCLE EXPANDER CPU RESET SMALL/LARGE
NTAK
L /M IO Q S0 B S0, QS1
RD UBE WR
I A PUT/OUTPUT N D0 - AD15 RQ/AK0, RQ/AK1 O I THER C
; ; ; ; ; ; ; ; ; ; ; ; ; ;
ADDRESS BUS/PROCESSOR STATUS ADDRESS STROBE BUS STATUS BUFFER ENABLE BUFFER READ/WRITE BUS LOCK HOLD ACKNOWLEDGE INTERRUPT ACKNOWLEDGE IO/MEMORY LATCHED BUS STATUS 0 (UPD70108/H) QUEUE STATUS READ STROBE UPPER BYTE ENABLE (UPD70116/H) WRITE STROBE
ADDRESS/DATA BUS ; HOLD REQUEST IN/ACKNOWLEDGE OUT ; INTERNALLY CONNECTED
UPD70108HGC(3/3)
1 - 3, 51 4, 10 - 17 A16/PS0 - A19/PS3 12 A8 - A15 8 18 - 25 38, 39 LBS0 * 41 - 44 BUFEN (BS0), 48, 50 BUFR/W (BS1) 8 IO/M (BS2) AD0 - AD7
INTERNAL ADDRESS/DATA BUS(20)
BUS BUFFER
ADM STATUS CONTROL
49
ATSB (QS0),
INTAK (QS1) RD, WR (BUSLOCK)
S/LG READY RESET POLL HLDRQ (RQ/AK0) HLDAK (RQ/AK1) NMI INT
PS SS DS0 DS1 PFP DP TEMP Q0 Q1 Q2 Q3
36 35 37 47
T-STATE CONTROL CYCLE DECISION
BUS HOLD CONTROL INTERRUPT CONTROL
45 28 29
QUEUE CONTROL
STANDBY CONTROL
30
CLK BCU EXU
QUEUE DATA BUS (8)
TC
SUB DATA BUS (16)
TA SHIFTER TB
MAIN DATA BUS (16)
LC PC AW BW CW DW IX IY BP SP
EFFECTIVE ADDRESS GENERATOR
µADDRESS REGISTER
µINSTRUCTION STORAGE µSEQUENCE CONTROL
MICRO DATA BUS
INSTRUCTION DECODER
(ALU) ARITHMETIC LOGIC UNIT UPD70108, 70108H ; LBS0 (HIGH) UPD70116, 70116H ; UBE
PSW
*
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