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Details, datasheet, quote on part number:WD8110LVZZ
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Datasheet text preview:
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I D8110LVZZ(1/3) W L16
C-MOS SYSTEM CONTROLLER FOR 80486SX/DX
-TOP VIEW156 150 140 130 120 110 105
GND
VDD3V
GND
GND
157 160
GND
104 100
GND 170 VDD3V
GND
90 VDD3V
180
GND
GND
80
190
VDD3V GND
VDD3V
70
GND 200 GND
60
VDD5V
VDD5V
GND
208
GND
GND
53
1
10
20
30
40
50 52
WD8110LVZZ(2/3) (VDD3V = +3.3 to 5V, VDD5V = +5V) INPUT N PIN SIGNAL I/O SIGNAL O. 1X/2X ; SINGLE/DOUBLE PHASE CPU CLOCK C AS11 166 I GND D 3VBUFFER ; 3VOLT BUFFER A S10 A 167 I/O D9 AVCORE ; 3VOLT CORE A27 ; PROCESSOR ADDRESS BUS (80486 AND 80386DX MODE) WS D 168 I/O D10 BDS ; ADDRESS STATUS D /R 169 I/O D 11 BCLK2 ; BUS CLOCK M /C 170 I/O D12 BE0-3 ; BYTE ENABLE 0-3 (80386DX OR 80486 MODE) P /IO 171 I/O D13 CLAST ; BLAST (80486 MODE) LDREF 172 /O V 14 CLK14 ; CLOCK 14 (14.318MHz) G S32 D 173 I DD3V DLKTEST ; CLOCK TEST D/C ; DATA CONTROL P ND 174 I/O D15 FS RDY ; DFS READY FOR IBM CPUS S MCIN 175 I/O D16 E DRQ0-3,5-7 ; DRQ D USPA 176 I/O D17 F XCOP ; EXTERNAL 80387 CO-PROCESSOR FS RDY 177 I/O D18 HERR ; FLOATING POINT ERROR (80486 MODE) PB HK486 C 178 I/O D19 I OLDA ; HOLD ACKNOWLEDGE IOCHRDY ; I/O CHANNEL READY R LAST 179 I/O D20 IOCK ; I/O CHANNEL CHECK RA0/ED0 180 /O G 21 IOCS16 ; 16-BIT I/O CYCLE RA1/ED1 181 I DND L QSET0,1 ; INTERRUPT REQUEST SET0,1 R V 2/ED2 A 182 I/O D22 M S32 D ; LOCAL DATA SIZE 32 R DD3V 183 I/O D23 M/IO ; MEMORY OR I/O MASTER ; MASTER RA3A/CS3 184 I/O D24 MEMCS16 ; 16-BIT MEMORY CYCLE R 3B/CS4 A 185 I/O D25 N ODE486 ; 80386/80486 MODE RA4/ED3 186 I/O D26 NPBUSY ; NUMERIC PROCESSOR BUSY RA5/ED4 187 I/O D27 OPERR ; NUMERIC PROCESSOR ERROR (80386 MODE) RA6/ED5 188 I/O D28 P SCIN ; OSCILLATOR IN A7/ED6 G 189 /O V 29 PCHK486 ; PARITY CHECK 80486 PDREF ; POWER DOWN REFRESH R ND 190 I DD3V RMCIN ; POWER MANAGEMENT CONTROL RA8/ED7 191 I/O D30 RDYIN ; PROCESSOR READY IN R A9/CS0 192 /I O I 31 S STIN ; SYSTEM RESET RA10/CS1 193 RQSET0 G SMIACT ; SYSTEM MANAGEMENT INTERRUPT ACTIVE FOR INTEL CPU A11/CS2 1 194 I I ND SMIADS ; SYSTEM MANAGEMENT INTERRUPT ADDRESS STROBE FOR AMD AND SYRIX CPU S USPA ; SUSPEND ACKNOWLEDGE FOR CYRIX CPUS A X/2X 195 I S QSET1 R SXA1 ; SX PROCESSOR ADDRESS BIT 1 (80386SX MODE) R 0GATE 2 196 I SMIADS SXBHE ; SX BUS HIGH ENABLE (80386SX MODE) C DY486 I H IACT M SXBLE ; SX BUS LOW ENABLE (80386SX MODE) LKTEST C 197 I R LDA O WM X ; 80386SX OR 386/486 MODE SELECT T SEN 198 O H STIN W/R ; WRITE OR READ MC 299 O S LDR O WTKIRQ13 ; WEITEK IRQ13 (IN WEITEK MODE) Z TKMODE ; WEITEK MODE MXCTL0 200 I D KR P EROWS ; ZERO WAIT STATE MXCTL1 201 /O G P0 XD TL2 C D0 D1 D2 D3 D4 D5 D6 D7 8 202 203 204 205 206 207 08 I I/O I/O O /O O O O DND DP1 DP2 E P3 G XBUSY PB EGRD R D S16 ACKEN
N PIN O. 2 1 3 4 5 6 7 8 9 1 10 11 12 13 14 15 16 17 18 29 20 21 22 23 24 25 26 27 28 39 30 31 32 33 34 35 36 37 38 49 40 41 42 43 44 5
I/O O O O O I I/O I/O I/O I/O I/O I/O I/O I/O /O I I/O /O I I/O I/O I/O I/O /I O I I I I I I I I I I I I I I O I /O I I/O I/O I/O /O
SIGNAL B EN A S ALE L YSCLK S WMEG O S EMR M SD15 SD14 SD13 SD12 S D11 S 10 D SD9 SD8 GD7 SND SD6 V D5 DD5V S SD4 SD3 SD2 SD1 C D0 M LK14 ASTER I I OCK Z CHRDY O EG OWS R M ND IEMCS16 OCS16 D DRQ7 DRQ6 DRQ5 DRQ3 DRQ2 V RQ1 D D5V D W RQ0 S KIRQ13 T R MEMW EGRESH F S ND LBHE I A20 IOW OR
N PIN O. 46 47 48 59 50 51 52 53 54 55 56
I/O I/O I/O I/O O /O O O O O I O /O I O /O O O I O I I/O I/O I/O I/O I/O I/O I/O /O I I/O I/O I/O /O I I/O I/O I/O I/O I/O I/O I/O /O I I/O I/O I/O I/O /I O I
SIGNAL MEMW M S MR E SA1 M A0 MDEN N IR D D MI IRMWR NTRQ A S 31 XLOWEN A S 29 S USP TP REQ DFS REQ S A27 XSWPEN A A26 A25 A24 A23 A22 A21 A20 G 19 AND A18 A17 A16 V 15 DD3V A A14 A13 A12 A 11 A0 1 A9 A8 G7 AD N A6 A5 A4 A3 R2 B YIN D E3
N PIN O. 88 99 90 91 92 93 94 95 96 97 98 19 100 101
I/O I I I I I I I I O I O I O I O I O O O I O O I /I O O I I O O I O O O O O O O O O O O O
SIGNAL VDD3V B S E2 B A1 X S E1 XBHE B S E0 N XBLE F ERR P B ERR N DY486 R G PBUSY PREGWR G 3 ND R BUFFER V 3OMBA16 R VCORE OS BA17 M R XM C MBA18 O N URES P W PRST S KMODE T F IRDY M LUSH S M MI ODE486 K B EN OCLK2 C SCIN L UCLK P E BCLK E COP X G DS A R ND RAS0 RAS1 RAS2 RAS3 C AS4 CAS03 G S02 A C ND CAS01 V AS00 CDD3V CAS13 AS12
N PIN O. 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153
I/O O I I I I I I I I I I I I I/O I/O /O O O I I/O I/O I/O /O I O /O O O I O O I O O O O O I I/O I/O I/O I/O I/O I/O I/O I/O /O
57 58 69 60 61 62 63 64 65 66 67 68 79 70 71 72 73 74 75 76 77 78 89 80 81 82 83 84 85 86 7
102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 22
154 155 156 157 158 159 160 161 162 163 164 65
WD8110LVZZ(3/3) OUTPUT ; A20 GATE ; ADDRESS ENABLE ; AT BUS ADDRESS LATCH ENABLE ; BURST READY 80486 ; BUS SIZE 16 ; COLUMN ADDRESS SELECT 0 ; COLUMN ADDRESS SELECT 1 ; 386/486 CPU CLOCK ; CPU RESET ; CHIP SELECT ENABLE ; DACK ENABLE ; DYNAMIC FREQUENCY SHIFT REQUEST FOR IBM BL CPU (NOT IN WEITEK MODE) ; DRAM WRITE ; EXTERNAL ADDRESS VALID ; EXTENDED COPROCESSOR BUSY (EXTERNAL COPROCESSOR MODE) ; FLUSH CACHE ; GENERAL PURPOSE REGISTER IO READ (NOT IN EXTERNAL COPROCESSOR MODE) ; GENERAL PURPOSE REGISTER IO WRITE H PREGWR ; HOLD REQUEST I OLDR ; INTERRUPT REQUEST K TRQ N ; CACHE ENABLE L EN ; LOCAL BUS CLOCK LBCLK ; FIRST MEGABYTE (IN WEITEK MODE) M WMEG O ; MEMORY DATA ENABLE MDEN ; MEMORY DIRECTION MDIR ; MULTIPLEXER CONTROL N XCTL0-2 ; NON-MASKABLE INTERRUPT NMI ; NUMERIC PROCESSRO RESET RPRST RA9-11,3A,3B/CS0-4 ; DRAM ADDRESS BITS/ CHIP SELECT BITS ; ROW ADDRESS SELECT RAS0-4 ; READY 80486 RDY486 ; ROM BANK SWITCH S OMBA16-18 ; S MEMORY READ (NOT IN WEITEK MODE) SMEMR ; S MEMORY WRITE (NOT IN WEITEK MODE) SMEMW ; SYSTEM MANAGEMENT INTERRUPT READY SMIRDY ; SPEAKER SPKR ; STOP CLOCK REQUEST FOR INTEL CPUS (NOT IN WEITEK MODE) TP REQ ; SUSPEND FOR CYRIX CPUS (NOT IN WEITEK MODE) SUSP ; SXLOWEN (80386SX MODE) SXLOWEN ; SXSWPEN (80386SX MODE) SXSWPEN ; SYSTEM CLOCK T YSCLK ; TERMINAL COUNT C A 20GATE BEN BALE BRDY486 CS16 CAS00-03 CAS10-13 CPUCLK CPURES DSEN DACKEN FS REQ E DRMWR EADS F XBUSY GLUSH GPREGRD INPUT/OUTPUT A2-26,29,31 D0-31 I P0-3 IOR LW O M 20 A MEMR R EMW RA0-2,4-8/ED0-7 S EFRESH SA0,1 SBHE SD0-15 MI ; PROCESSOR ADDRESS BUS DATA BUS ; DATA PARITY ; I/O READ ; I/O WRITE ; EARLY ADDRESS 20 ; REMORY READ ; MEMORY WRITE ; DRAM ADDRESS BITS/ EDATA BITS ; REFRESH ; SYSTEM ADDRESS 0,1 ; SYSTEM BUS HIGH ENABLE ; AT DATA BUS ; SYSTEM MANAGEMENT INTERRUPT
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