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Part: X24CO4PC7187

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Description: Ic-4k Serial CMOS EePROM

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Datasheet: Download X24CO4PC7187 datasheet     File size : 1333 kB

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Datasheet text preview:
X24C04 4K
X24C04
Serial E2PROM
512 x 8 Bit
FEATURES
DESCRIPTION The X24C04 is a CMOS 4096 bit serial E2PROM, internally organized 512 x 8. The X24C04 features a serial interface and software protocol allowing operation on a simple two wire bus. The X24C04 is fabricated with Xicor's advanced CMOS Textured Poly Floating Gate Technology. The X24C04 utilizes Xicor's proprietary DirectWriteTM cell providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
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1.8V to 3.6V, 2.7V to 5.5V Power Supply Versions Low Power CMOS --Active Read Current Less Than 1 mA --Active Write Current Less Than 1.5 mA --Standby Current Less Than 1 µA Internally Organized 512 x 8 2 Wire Serial Interface --Bidirectional Data Transfer Protocol --Schmitt Trigger Input Noise Suppression 400Khz across VCC range Sixteen Byte Page Write Mode --Minimizes Total Write Time Per Byte Self Timed Write Cycle --Typical Write Cycle Time of 5 ms High Reliability --Endurance: 100,000 Cycles --Data Retention: 100 Years 8 Pin Mini-DIP, 8 Pin SOIC, 8 pin MSOP and 8 pin TSSOP
FUNCTIONAL DIAGRAM
(8) VCC (4) VSS (7) TEST START CYCLE (5) SD A START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER +COMPARATOR XDEC E2 PROM 128 X 128 H.V. GENERATION TIMING & CONTROL
(6) SCL (3) A 2 (2) A 1 (1) A 0
LOAD
INC
WORD ADDRESS COUNTER R/W YDEC 8 CK PIN DOUT ACK DATA REGISTER DOUT
ÓXicor, 1995, 1996 Patents Pending 6551-2.5 2/24/99 T1/C10/D0 NS
1
Characteristics subject to change without notice
X24C04
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the PullUp Resistor selection graph at the end of this data sheet. Address (A0, A1, A2) A0 is a no connect. The Address inputs (A1, A2) are used to set the appropriate bits of the seven bit slave address. These inputs can be used static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If driven they must be driven to VSS or to VCC. Write Protect (WP) The write protect pin provides Hardware Write Protection. When held low Hardware Write Protection is disabled; when connected to VCC, the write protection feature is enabled and the whole array is write-proptected. PIN NAMES Symbol
A0­A2 SDA SCL WP VSS VCC
A0 A1 A2 VSS
PIN CONFIGURATION
DIP/SOIC/MSOP 1 2 3 4 X24C04 8 7 6 5 VCC WP SCL SDA
8-LEAD TSSOP WP VCC A0 A1 1 2 3 4 X25138 8 7 6 5 SCL SDA VSS A2
Description
Address Inputs Serial Data Serial Clock Write Protect Ground Supply Voltage
2
X24C04
DEVICE OPERATION The X24C04 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24C04 will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reser ved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C04 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA DATA STABLE DATA CHANGE
Figure 2. Definition of Start and Stop
SCL
SDA START BIT STOP BIT
3


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