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Details, datasheet, quote on part number:XL24C01AY
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Datasheet text preview:
EXEL Microelectronics, Inc.
XL24C01A
1,024-Bit Serial Electrically Erasable PROM 2.7 To 5.5 Volt Operation
FEATURES · Low Power CMOS -- Active current less than 2mA -- Standby current less than 2µA · Hardware Write Protection -- Write Control pin · 2.7V to 5.5V Operation · · · Extended Temperature Range: -40°C to +85°C Internally Organized as 128 x 8
JEDEC Small Outline "Y" Package A0 1 A1 2 V23
SS 4
PIN CONFIGURATIONS
Plastic Dual-in-line "P" Package A0 1 A1 2 V2 3
SS 4
8 VCC W 7 SC 6 SCL 5
DA
Two Wire Serial Interface (I2CTM) -- Bidirectional data transfer protocol · Four-Byte Page-Write Mode -- Minimizes total write time per byte · Automatic Word Address Incrementing -- Sequential register read · Self-Timed Write Cycle · High Reliability -- Endurance: 100,000 erase/write cycles -- Data retention: 100 years · 8-Pin PDIP or SOIC Packages
8 VCC W 7 SC 6 SCL 5
DA
D0013 ILL A01.1
PIN NAMES A0-A2 SDA SCL WC VSS VCC Address Inputs Serial Data I/O Serial Clock Input Write Control Input Ground Supply Voltage
OVERVIEW The XL24C01A is a cost effective 1,024-bit serial E2 PROM. It is fabricated using EXEL's advanced CMOS E2 PROM technology. This part operates from a single supply over the range of 2.7 to 5.5 volts. The XL24C01A is internally organized as a 128 x 8 memory bank. It features a I2C serial interface and software protocol allowing operation on a simple two-wire bus. Up to eight XL24C01A s may be connected to the 2wire bus by establishing their device address using the address input pins (A0, A1 and A2). PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable when SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL.
Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output, and may be wire-ORed with any number of open-drain or open-collector outputs. Address (A0, A1 and A2) - The address inputs are used to set the three bit device address of the XL24C01A which will identify it on the two-wire bus. These inputs may be tied HIGH or LOW, or they may be actively driven. These inputs allow up to eight XL24C01A devices to be distinguished on the bus. Write Control (WC) - The Write Control input pin is used to disable write circuitry to the memory. When HIGH, the write function is disabled, protecting previously written data; when LOW, the write function is enabled.
2 XEL Microelectronics, Inc. E P 50 Commerce Drive · San Jose, CA 95131 1 hone 408 432-0500 · Fax 408 432-8710 · Internet www.exel.com
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XL24C01A
BLOCK DIAGRAM
Vcc SDA SCL WC
8 5 6 7
Slave Address Register & Comparator
High Voltage Gen., Timing and Control
Control L ogic
32 x 32 MCmory e ore
A2 3 A1 2 A0 1 Vss 4
Load
Inc.
32
Word Address Counter
DY ecoder
ACK
Clock
D I/O
Data Register
D0013 ILL B01.1
ENDURANCE AND DATA RETENTION The XL24C01A is designed for applications requiring up to 100,000 write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 write cycles. APPLICATIONS The XL24C01A is ideal for high volume applications requiring low power and low density storage. This device uses a cost effective, space-saving 8-pin plastic package. Typical applications include robotics, alarm devices, electronic locks, meters and instrumentation. CHARACTERISTICS OF THE I2C BUS General Description The I2C bus was designed for two-way, two-line serial communication for different integrated circuits. The two lines are: a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (See Figure 1). Data transfer between devices may be initiated with a START condition only when SCL and SDA are HIGH (bus is not busy). Input Data Protocol One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the clock
HIGH time, because changes on the data line, while SCL is HIGH will be interpreted as "START" or "STOP" condition (See Figure 2). START and STOP Conditions When both data and clock lines are HIGH, the bus is known as "not busy." A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the "START" condition. A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the "STOP" condition (See Figure 3). DEVICE OPERATION The XL24C01A is a 1,024-bit serial E2 PROM. The device supports the I2 C bidirectional data transmission protocol. The protocol defines any device that sends data onto the bus as a "transmitter" and the receiving device as the "receiver." The device controlling the data transmission is the "master" and the controlled device is the "slave." In all cases, the XL24C01A will be a "slave" device, since it never initiates any data transfers. Up to eight XL24C01As can be connected to the bus, selected by the A0, A1 and A2 device addresses. A0, A1 and A2 must be connected to either VCC, VSS or they may be actively driven. A0, A1 and A2 define the device address. Other devices may be connected to the bus, but need a different device identification code.
D0013 3/96 DVPTD 6931-05
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DX ecoder
32
XL24C01A
Vcc
SDA SCL
T Master ransmitter/ R eceiver RSlave eceiver T Slave ransmitter/ R eceiver T Master ransmitter T Master ransmitter/ R eceiver
(24C01A)
(µC/ µP)
D0013 ILL F01.2
FIGURE 1. TYPICAL SYSTEM CONFIGURATION
SCL
Data must remain stable w ihile clock s HIGH.
Change o f data allowed
Data must remain stable w ihile clock s HIGH.
SDA In tHD:DAT tSU:DAT tHD:DAT
D0013 ILL F02.2
FIGURE 2. INPUT DATA PROTOCOL
SCL
START Condition STOP Condition
SDA In
D0013 ILL F03.2
FIGURE 3. START AND STOP CONDITIONS
3
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