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Details, datasheet, quote on part number:XL24C04
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Datasheet text preview:
EXEL Microelectronics, Inc.
XL24C04
4,096-Bit Serial Electrically Erasable PROM 2.7 to 5.5 Volt Operation
FEATURES · Low Power CMOS -- Active current less than 3mA -- Standby current less than 5µA · Hardware Write Protection -- Write Control pin · 2.7 to 5.5V Operation · · Extended Temperature Range: -40°C to +85°C Internally Organized as Two Banks -- Each 256 x 8 · Two Wire Serial Interface (I2CTM) -- Bidirectional data transfer protocol · Sixteen-Byte Page-Write Mode -- Minimizes total write time per byte · Automatic Word Address Incrementing -- Sequential register read · Self-Timed Write Cycle · High Reliability -- Endurance: 100,000 write cycles -- Data retention: 100 years · 8-Pin PDIP or SOIC Packages OVERVIEW T h e XL24C04 is a cost-effective, 4,096-bit serial E2 PROM. It is fabricated using EXEL's advanced CMOS E2 PROM technology. This part operates from a single power supply over the range of 2.7 to 5.5 volts. The XL24C04 is internally organized as two 256 x 8 memory banks. It features the I2C serial interface and software protocol allowing operation on a simple two-wire bus. Up to four XL24C04s may be individually addressed on the two-wire bus by establishing their device address using the address input pins (A1 and A2). PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP PIN CONFIGURATIONS
Plastic Dual-in-line "P" Package A0 1 A1 2 V2 3
SS 4
8 VCC W 7 SC 6 SCL 5
DA
JEDEC Small Outline "Y" Package A0 1 A1 2 V23
SS 4
8 VCC W 7 SC 6 SCL 5
DA
D0015 ILL A01.1
PIN NAMES A0-A2 SDA SCL WC V SS V CC Address Inputs Serial Data I/O Serial Clock Input Write Control Input Ground Supply Voltage
conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector outputs. Address (A0) - The A0 pin is not electrically connected internally. It can be connected to VSS or left floating. It must not be connected to VCC. Address (A1, A2) - The address input pins are used to set the two-bit device address of the XL24C04 which will identify it on the two-wire bus. These inputs may be tied HIGH, LOW, or they may be actively driven. These inputs allow up to four XL24C04 devices to be distinguished on the bus. Write Control (WC) - The Write Control input pin is used to disable the write circuitry to the memory. When HIGH, the write function is disabled, protecting previously written data; when LOW, the write function is enabled.
2 EXEL Microelectronics, Inc. P 50 Commerce Drive · San Jose, CA 95131 1 hone 408 432-0500 · Fax 408 432-8710 · Internet www.exel.com
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XL24C04
BLOCK DIAGRAM
Vcc SDA SCL WC
8 5 6 7
Slave Address Register & Comparator
High Voltage Gen., Timing and Control
Control L ogic
32 x 128 MCmory e ore
A2 3 A1 2 A0 1 Vss 4
C No onnect
Load
Inc.
128
Word Address Counter
DY ecoder
ACK
Clock
D I/O
Data Register
D0015 ILL B01.1
ENDURANCE AND DATA RETENTION The XL24C04 is designed for applications requiring up to 100,000 write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 write cycles. APPLICATIONS The XL24C04 is ideal for applications requiring low voltage and low power consumption. This device uses a cost effective, space-saving, 8-pin plastic package. Typical applications include, alarm devices, electronic locks, meters, keys, pagers and cellular phones. CHARACTERISTICS OF THE I2C BUS General Description The I2C bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are: a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (See Figure 1). Data transfer between devices may be initiated with a START condition only when SCL and SDA are HIGH (bus is not busy).
Input Data Protocol One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock HIGH time, because changes on the data line while SCL is HIGH will be interpreted as start or stop condition (See Figure 2.) START and STOP Conditions When both the data and clock lines are HIGH, the bus is said to be not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is defined as the "START" condition. A LOW-to-HIGH transition on the data line, while the clock is HIGH, is defined as the "STOP" condition (See Figure 3.) DEVICE OPERATION The XL24C04 is a 4,096-bit serial E2PROM. The device supports the I2 C bidirectional data transmission protocol. The protocol defines any device that sends data onto the bus as a "transmitter" and any device which receives data as a "receiver." The device controlling data transmission is called the "master" and the controlled device is called the "slave." In all cases, the XL24C04 will be a "slave" device, since it never initiates any data transfers. Up to four XL24C04s can be connected to the bus, selected by the A1 and A2 device addresses. A0 is not connected internally. A1 and A2 must be connected to either VCC, VSS or they may be actively driven. A1 and A2 define the device address. Other devices may be connected to the bus, but need a different device identification code.
D0015 3/96 DVPTD 6931-06
2
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DX ecoder
32
XL24C04
Vcc
SDA SCL
T Master ransmitter/ R eceiver RSlave eceiver T Slave ransmitter/ R eceiver T Master ransmitter T Master ransmitter/ R eceiver
(24C04)
(µC/ µP)
D0015 ILL F01.2
FIGURE 1. TYPICAL SYSTEM CONFIGURATION
SCL
Data must remain stable w ihile clock s HIGH.
Change o f data allowed
Data must remain stable w ihile clock s HIGH.
SDA In tHD:DAT tSU:DAT tHD:DAT
D0015 ILL F02.2
FIGURE 2. INPUT DATA PROTOCOL
SCL
START Condition STOP Condition
SDA In
D0015 ILL F03.2
FIGURE 3. START AND STOP CONDITIONS
3
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