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Details, datasheet, quote on part number:XL24C08Y
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Datasheet text preview:
EXEL Microelectronics, Inc.
XL24C08
8,192-Bit Serial Electrically Erasable PROM 1.8 to 5.5 Volt Operation
FEATURES · Low Power CMOS -- Active current less than 3mA -- Standby current less than 5µA · Hardware Write Protection -- Write Control pin · Industry's lowest power 8K E2PROM · High reliability -- All commercial devices tested to industrial temp range (-40°C to +85°C) True Philips licensed I2C interface Internally Organized 1,024 X 8 PIN CONFIGURATIONS
Plastic Dual-in-line "P" Package A0 1 A1 2 V2 3
SS 4
8 VCC W 7 SC 6 SCL 5
DA
· · ·
JEDEC Small Outline "Y" Package A0 1 A1 2 V23
SS 4
8 VCC W 7 SC 6 SCL 5
Two Wire Serial Interface (I2CTM) -- Bidirectional data transfer protocol -- Standard 100KHz and Fast 400KHz · Sixteen-Byte Page-Write Mode -- Minimizes total write time per byte · Automatic Word Address Incrementing -- Sequential register read · Self-Timed Write Cycle · High Reliability -- Endurance: 100,000 erase/write cycles -- Data retention: 100 years · 8-Pin PDIP or SOIC Packages
DA
D0016 ILL A01.2
PIN NAMES A0, A1 A2 SDA SCL WC VSS VCC Unused Address Inputs Device Select Input Serial Data I/O Serial Clock Input Write Control Input Ground Supply Voltage
OVERVIEW T h e XL24C08 is a cost-effective, 8,192-bit serial E2 PROM. It is fabricated using EXEL's advanced CMOS E2 PROM technology. This part operates from a single power supply over the range of 1.8 to 5.5 volts. The XL24C08 is internally organized as 1,024 x 8. It features the I2CTM serial interface and software protocol allowing operation on a simple two-wire bus. PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector outputs. Address Inputs (A0, A1) - The A0 and A1 inputs are unused by the XL24C08; however, to insure proper operation they can be unconnected or tied to ground. They must not be tied to VCC. Address Input (A2) - The A2 input is unused to set the appropriate bit of the seven bit slave address. It may be actively driven or tied to VCC or VSS. It cannot be a no connect.
2 EXEL Microelectronics, Inc. P 50 Commerce Drive · San Jose, CA 95131 1 hone 408 432-0500 · Fax 408 432-8710 · Internet www.exel.com
D0016 3/96 DVPTD 6931-04
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XL24C08
BLOCK DIAGRAM
Vcc SDA SCL WC
8 5 6 7
Slave Address Register & Comparator
High Voltage Gen., Timing and Control
Control L ogic
128 x 128 MCmory e ore
A2 3 A1 2 A0 1 Vss 4
Load
Inc.
128
Word Address Counter
DY ecoder
ACK
Clock
D I/O
Data Register
D0016 ILL B01.1
Write Control (WC) - The Write Control input pin is used to disable the write circuitry to the memory. This input must be tied HIGH, LOW, or left unconnected. When HIGH, the write function is disabled, protecting previously written data; when LOW or unconnected, the write function is enabled. ENDURANCE AND DATA RETENTION The XL24C08 is designed for applications requiring up to 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. APPLICATIONS The XL24C08 is ideal for applications requiring low voltage and low power consumption. This device uses a cost effective, space-saving, 8-pin plastic package, SOIC and PDIP. Typical applications include alarm devices, electronic locks, meters, keys, pagers and cellular phones.
CHARACTERISTICS OF THE I2C BUS General Description The I2C bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are: a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (See Figure 1). Data transfer between devices may be initiated with a START condition only when SCL and SDA are HIGH (bus is not busy). Input Data Protocol One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock HIGH time, because changes on the data line while SCL is HIGH will be interpreted as start or stop condition (See Figure 2). START and STOP Conditions When both the data and clock lines are HIGH, the bus is said to be not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is defined as the "START" condition. A LOW-to-HIGH transition on the data line, while the clock is HIGH, is defined as the "STOP" condition (See Figure 3).
D0016 3/96 DVPTD 6931-04
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DX ecoder
128
XL24C08
Vcc
SDA SCL
T Master ransmitter/ R eceiver RSlave eceiver T Slave ransmitter/ R eceiver T Master ransmitter T Master ransmitter/ R eceiver
(24C08)
(µC/ µP)
D0016 ILL F01.1
FIGURE 1. TYPICAL SYSTEM CONFIGURATION
SCL
Data must remain stable w ihile clock s HIGH.
Change o f data allowed
Data must remain stable w ihile clock s HIGH.
SDA In tHD:DAT tSU:DAT tHD:DAT
D0016 ILL F02.2
FIGURE 2. INPUT DATA PROTOCOL
SCL
START Condition STOP Condition
SDA In
D0016 ILL F03.2
FIGURE 3. START AND STOP CONDITIONS
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