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Details, datasheet, quote on part number:XL25026P
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Datasheet text preview:
EXEL Microelectronics, Inc.
XL25026
2,048-Bit Serial Electrically Erasable PROM Synchronous Peripheral Interface 2.7 to 5.5 Volt Operation
FEATURES · Motorola SPI (Modes 0 and 3) and SIOP Compatible · · · 1 MHz Clock Rate Extended Temperature Range: -40°C to +85°C
PIN CONFIGURATIONS
Plastic Dual-in-line "P" Package
CS 1 SCK 2 SI 3 SO 4 8 VCC 7 R/B 6 WC
Low Power Consumption -- Active current 500µA -- Standby current 2µA · 2.7 to 5.5 volt operation (both READ and WRITE) · Hardware & Software Write Protection -- Defaults to disabled state at power up -- Software instructions for WRITE-enable/ disable · Internally Organized as 128 x 16 bits · Easy-to-Use Interface -- READY/BUSY status signal -- Automatic write cycle time-out High Reliability -- Endurance: 100,000 erase/write cycles -- Data retention: 100 years 8-Pin PDIP or SOIC Packages
5 GND
EIA" Small Outline J F" Package
R/B 1 VCC 2 CS 3 SCK 4 8 WC 7 GND 6 SO 5 SI
D0028 ILL A01.2
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PIN NAMES CS SCK SI SO GND WC R/B Vcc Chip Select Input Serial Clock Input Serial Input Serial Output Ground Write Control Input READY/BUSY Output Power Supply
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OVERVIEW The XL25026, a member of the SPI LiteTM memory family, is a cost effective 2,048-bit, nonvolatile, serial E 2PROM designed to directly interface with the Motorola SIOP and SPI ports. The XL25026 provides external read/write memory arranged as 128 registers of 16 bits each. Four 8-bit instructions control the operation of the device, which include read, write, write enable and write disable. The READY/BUSY pin indicates the status of the device when polled during the WRITE operation. The serial data output pin (SO) also indicates the status of the device during the self-timed nonvolatile programming cycle. To protect against inadvertent writes, the WRITE instruction is accepted only while the chip is in the write enabled state. After the initiation of the write cycle, if Chip Select (CS) is brought LOW, while SCK is low, the SO pin will indicate the READY/BUSY status of the chip.
2 EXEL Microelectronics, Inc. P 50 Commerce Drive · San Jose, CA 95131 1 hone 408 432-0500 · Fax 408 432-8710 · Internet www.exel.com
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XL25026
BLOCK DIAGRAM
O I INR TRUCTION S EGISTER
R DATA AEGISTER
A /W R MPS
D
WS C SC SK C
INSTRUCTION D C ECODE, OA TROL N C ND G LOCK ENERATION
R DDRESS EGISTER
DLOW
DDDRESS A ECODER
E PROM ( ARRAY 128 X 16) S
2
W
VCC ETECTOR HIGH VOLTAGE GENERATOR
E RITE NABLE
R/B
0028 ILL B01.2
ENDURANCE AND DATA RETENTION The XL25026 is designed for applications requiring up to 100,000 erase/write cycles. It provides 100 years of secure data retention, with or without power applied. DEVICE OPERATION The XL25026 is a synchronous serial port compatible E2 PROM. It operates on a single power supply ranging from 2.7V to 5.5V and it has an on-chip voltage generator to provide the high voltage needed during a programming operation. Input data is latched on the rising edge of the clock (SCK), and data is output on the falling edge of the clock. Data is grouped in 8-bit bytes. The beginning 8 bits specify the mode, the next 8 bits specify the address, and subsequent 16 bits specify the I/O data. Each instruction sent to the device includes a 4 bit start sequence, 1010, a 4 bit opcode and a 7-bit address including one dummy bit at the end. For a WRITE operation, a 16 bit data field is required following the 8 bit address field. The device requires an active LOW CS in order to be selected. Each instruction must be preceded by a HIGH-to-LOW transition of CS before the 4 bit start sequence is given. Prior to the 4 bit start sequence (1010), inputs of all other logical sequence are ignored.
During the self-timed internal programming cycle that accompanies a write, the SCK clock is deactivated. It is needed only when instructions or data are being passed to or from the memory. Any of the four modes (read, write, write enable, write disable) may be specified. The write time is set by an internal timer, and determination of whether a write operation is in progress or not can be made from the status of the READY/BUSY pin. Read (READ) The read instruction is the only instruction that outputs serial data on the SO pin. After the read instruction and address have been decoded, data is transferred from the selected memory register into the output register. The output on SO changes during the HIGH to LOW transition of SCK. Write (WRITE) After a write instruction and its address have been decoded, the device expects 16 bits of data. These are to be transferred into the specific memory register which has previously been automatically erased. After the last data bit has been clocked into SI on the 32nd clock edge, the self-timed internal programming cycle is initiated. The write cycle status can be monitored by observing the READY/BUSY pin. It will output the BUSY status (LOW) within 1µs after the rising edge of the 32nd clock (the last
D0028 5/96 DVPTD 6931-04
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XL25026
data bit) and will stay LOW until the WRITE cycle is complete. It will then output a HIGH status until the next WRITE cycle is initiated. CS must be held HIGH for the minimum of tCS before the next instruction is entered. Another way to get READY/BUSY status is from the SO pin. During a WRITE cycle, asserting a LOW on the CS pin will cause the SO pin to output the READY/BUSY status. It is necessary for SCK to be brought into a LOW state 500ns prior to CS going LOW. Asserting a HIGH on CS will put the SO pin in a high impedance state again. After the WRITE cycle is completed, the SO pin will output HIGH when the device is deselected. The first rising edge of the SI pin will reset SO back into the high impedance state. Write Control (WC PIN) WC The WC pin provides hardware write control. When WC pin is low, the chip is enabled to execute WRITE functions. When WC pin is high, all WRITE functions are locked out. The device shows ready status on the R/B pin and on the SO pin, if CS and SCK are low. In addition, if WC pin changes state during the write cycle, the write operation will be aborted not guaranteeing the data. The WC pin does not have any effect on the READ, WREN and WRDI operations. Write Enable/Disable When the XL25026 is powered up, it comes up in the write disabled state. In order to be programmable, it must receive an enable instruction. The device remains programmable until a disable instruction is entered, or until it is powered down. The disable instruction provides protection against inadvertent writes. Read operation is not affected by this command.
INSTRUCTION SET
Instruction READ WRITE Write Enable (WREN) Write Disable (WRDI) Start Bits 1010 1010 1010 1010 OP Code 1000 0100 0011 0000 Address Data (A6-A0) 0 (A6-A0) 0 XXXXXXXX XXXXXXXX
D0028 PGM T01.4
Input
D15-D0
3
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