|
Details, datasheet, quote on part number:XL25081
| |
Datasheet text preview:
EXEL Microelectronics, Inc.
XL25081
8K-bit SPI Nonvolatile Memory
Preliminary Information
FEATURES · Motorola SPI (Modes 0 and 3) and SIOP Compatible · · · 2MHz Data Transfer Rate Low Power CMOS
PIN CONFIGURATIONS
Plastic Dual-in-line "P" Package
CS 1 SO 2 NC 3 GND 4 8 VCC 7 NC
Active Current - Less than 3mA -- Standby Current @ 5.5V Vcc - 5µA -- Standby Current @ 1.8V Vcc - 1µA · Direct Interface SPI Bus Configuration · Early End of Write Detection -- Status Register Polling · Software Controlled Inadvertent Write Protection · High Reliability -- Endurance - 100,000 minimum write cycles -- Data Retention - Greater than 100 years · Automatic Address Increment (Sequential Read) · Extended (-40 to +85° C) and Automotive (-40 to +125° C) Temperature Ranges
6 SCK
·
8-pin PDIP and 8-pin SOIC (JEDEC)
OVERVIEW
The XL25081, a member of the SPI LiteTM memory family, is a low cost, low power CMOS serial nonvolatile memory which is fully compatible with the synchronous peripheral interface (SPI Bus) developed by Motorola. The XL25081 is fully operational from 1.8V to 5.5V over the full industrial temperature range of -40°C to +85°C. The XL25081 has been designed for full operation at 5V ±10% over an extended automotive temperature range of -40°C to +125°C.
P
e r
m i l
i
a n
CS 1 SO 2 NC 3 GND 4
JEDEC Small Outline " Y" Package
y r
5 5
SI
8 VCC 7 NC 6 SCK SI
D0032 ILL A01.1
PIN NAMES Function Chip Select Input Serial Data Output Not Connected Ground Serial Data Input Serial Clock Input Not Connected Power Supply
Pin Pin Name 1 CS 2 SO 3 NC 4 VSS 5 SI 6 SCK 7 NC 8 VCC
The XL25081 is organized 1K x 8 and supports SPI operating modes 0,0 and 1,1. In addition it supports data transfer rates up to 2M-bits per second. PIN DESCRIPTIONS Serial Output (SO) During a read cycle, data is shifted out on the SO pin. Data is clocked out by the falling edge of the serial clock.
2 EXEL Microelectronics, Inc. P 50 Commerce Drive · San Jose, CA 95131 1 HONE 408 432-0500 · FAX 408 432-8710 · Internet www.exel.com
Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses or data present on the SI pin are latched on the rising edge of the clock while data on the SO pin change after the falling edge of the clock.
D0032 5/96 DVPTD 6931-05
XL25081
Preliminary Information
BLOCK DIAGRAM
RSTATUS EGISTER
X
D
SS K C S O CI S
COMMAND D ECODE & C ONTROL L OGIC
E C O D E
1K x 8 MEMORY A RRAY
C WRITE ONTROL Y DECODE & DATA REG
D0032 ILL B01.2
Chip Select (CS) CS When CS is HIGH, the XL25081 is deselected and the SO pin is at high impedance and unless an internal write operation is underway, the XL25081 will be in the standby power mode. CS LOW enables the XL25081 and places the device in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. BASIC DEVICE OPERATION The XL25081 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the popular 6805 and 68HC11 microcontroller families. Because of the 8-bit data format employed the XL25081 can also be easily interfaced to a large number of microcontroller serial ports.
Each device has an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be low during the entire operation of clocking the instruction, address and subsequent data transfer. The following table contains a list of the instructions, their opcodes and a description of the operation. Data input is sampled on the first rising edge of SCK after CS goes low. SCK is a static input and generally has no maximum duration either high or low; therefore, the user may stop the clock while servicing another interrupt.
Instruction
Instruction Format
Operation
WREN WRDI RDSR READ WRITE NO-OP
0000 0110 0000 0100 0000 0101 0000 0011 0000 0010 0000 0001
Set the Write Enable Latch (Enable Write Operations) Reset the Write Enable Latch (Disable Write Operations) Read Status Register Read Data From Memory Array at Selected Address Write Data to Memory Array at Selected Address Provides No-op in place of 25080 Write Status Register Instruction
D0032 PGM T01.1
D0032 5/96 DVPTD 6931-05
2
XL25081
Preliminary Information
Write Enable (WREN) and Write Disable (WRDI) The XL25081 contains a write enable latch. This latch must be SET before a nonvolatile write operation will be completed. The WREN instruction will set the latch and the WRDI instruction will reset the latch. The latch is automatically reset during power-on. Read Status Register (RDSR) The RDSR instruction provides access to the status register. The status register may be read at any time, even during a nonvolatile write cycle. The status register is formatted as follows: 7 1 6 1 5 1 4 1 3 1 2 1 1 WEL 0 WIP
D0032 PGM T02
Read Sequence The CS line is first pulled low to select the device. The 8bit opcode is set to the device and followed by the address to be read. After the read opcode and address are sent, the data stored at the selected memory location will be shifted out on the SO line. The data stored at the next higher address location can be read sequentially by continuing to provide clock pulses. Internally the address is automatically incremented to the next higher address after each byte of data is shifted out on the SO pin. When the highest address is reached the address counter will roll over to address 000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Write Sequence In order to write to the device the write enable latch must be set. The CS line is taken low and the 8-bit WREN instruction is clocked into the device. After the eighth clock CS must be returned high before issuing the WRITE opcode, address and data to be written. Once the write enable latch is set, the user may proceed by issuing the write instruction, address and then the data to be written. This is a thirty-two clock operation, CS must go low and remain low for the entire thirty-two clocks and must be brought high before a thirty-third clock is detected.
Bits 2 thru 7 are don't care and will be read as logic 1's. The Write-in-Process (WIP) bit indicates whether the device is busy with a write operation. When set to a "1" a write is in progress, when set to a "0" no write is in progress. The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When read as a "1" the latch is set, when read as a "0" the latch is reset. Clock and Data Timing Data input on the SI line is sampled and latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK.
[the write enable register will not be reset upon the completion of the write cycle]
3
D0032 5/96 DVPTD 6931-05
|
|
