|
Details, datasheet, quote on part number:XM20C64P
| |
Datasheet text preview:
XM20C64 64K
XM20C64
High Speed AUTOSTORETM NOVRAM
8K x 8
FEATURES
DESCRIPTION
The XM20C64 is a high speed nonvolatile RAM Module. It is comprised of four Xicor X20C16 high speed NOVRAMs, a high speed decoder and decoupling capacitors mounted on a co-fired multilayered Ceramic substrate. The XM20C64 is configured 8K x 8 and is fully decoded. The module is a 28-lead DIP conforming to the industry standard pinout for SRAMs. The XM20C64 fully supports the AUTOSTORE feature, providing hands-off automatic storing of RAM data into E2PROM when VCC falls below the AUTOSTORE threshold. The XM20C64 is a highly reliable memory component, supporting unlimited writes to RAM, a minimum 1,000,000 store cycles and a minimum 100 year data retention.
· · · · · · · · · · ·
High Speed: tAA = 55ns NO Batteries!! Low Power CMOS AUTOSTORETM NOVRAM --Automatically Stores RAM data to E2PROM upon Power-fail Detection Open Drain AUTOSTORE Output Pin --Provides Interrupt or Status Information --Linkable to System Reset Circuitry Auto Recall --Automatically Recalls E2PROM Data During Power-on Fully Decoded Module Full Military Temperature Range -- 55°C to +125°C High Reliability --Endurance: 1,000,000 Nonvolatile Store Cycles --Data Retention: 100 Years ESD Protection --2KV All Pins Also Available in 66 Pin PUMA Package
FUNCTIONAL DIAGRAM
2 25 31 23
PIN CONFIGURATION
NE
A0A10
NE OE WE
NE OE WE CE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE AS A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/04 I/O3
A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
I/O 30
2 A11 A12 2 3 A0 A1 Y0 Y1 Y2 Y3 CE 1 4 5 6 7 2 25 31 23 25 31 23
NE OE WE CE
A0A10
I/O 30
NE OE WE CE
A0A10
I/O 30
2 25 31 23 AUTOSTORE
AUTOSTORETM NOVRAM is a trademark of Xicor, Inc. ©Xicor, Inc. 1991, 1995, 1996 Patents Pending 3874-1.6 6/20/96 T0/C2/D0 NS
3874 FHD F02.1
NE OE WE CE
A0A10
A0A10
I/O 30
I/O0I/O7
3874 FHD F01
1
Characteristics subject to change without notice
XM20C64
PIN DESCRIPTIONS Addresses (A0-A12) The address inputs select an 8-bit memory location during read and write operations. Chip Enable (CE) CE The chip enable input must be LOW to enable all read, write and user requested nonvolatile operations. Output Enable (OE) OE During normal RAM operations OE controls the data output buffers. If a hardware nonvolatile operation is selected (NE = CE = LOW) and OE strobes LOW, a recall operation will be initiated. OE LOW will always disable a STORE operation regardless of the state of NE, WE, and CE so long as the internal transfer has not commenced. Write Enable (WE) WE During normal RAM operations WE = CE = LOW will cause data to be written to the RAM address pointed to by the A0-A12 inputs. Nonvolatile Enable (NE) NE The nonvolatile input controls the transfer of data from the E2PROM array to the RAM array, when strobed LOW in conjunction with CE = OE = LOW. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X20C64 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW. AUTOSTORE Output (AS) AS AS is an open-drain output. When it is asserted (driving LOW) it indicates VCC has fallen below the AUTOSTORE threshold and an internal store operation has been initiated. Because AS is an open drain output it may be wire-ORed with multiple open drain outputs and used as an interrupt input to a microprocessor. DEVICE OPERATION NOVRAM operations are identical to those of a standard SRAM. When OE and CE are asserted data is presented at the I/Os from the address location pointed to by the A0A12 inputs. RAM write operations are initiated and the address input is latched by the HIGH to LOW transition of CE or WE, whichever occurs last. Data is latched on the rising edge of either CE or WE, whichever occurs first. An array recall, E2PROM data transferred to RAM, is initiated whenever OE = NE = CE = LOW. A recall is also performed automatically upon power-up. Command Sequence Operations The X20C64 employs a version of the industry standard Software Data Protection (SDP). The end user can select various options for transferring data from RAM into the E2PROM array. All command sequences are comprised of three specific data/address write operations performed with NE LOW. A Store operation can be directly selected by issuing a Store command. The user may also enable and disable the AUTOSTORE function through the software data protection sequence. Refer to Table 1 below for a complete description of the command sequence. Operational Notes The X20C64 should be viewed as a subsystem when writing software for the various store operations. The module contains four discrete components each needing to be set to the required state individually. The two high order address bits (A11 and A12) select only one of the four components.
2
XM20C64
TABLE 1 Step 1 2 3 Operation Write Write Write A0A10* 555 2AA 555 Data Pattern AA 55 Command
3874 PGM T11
TABLE 2 Command CC[H] CD[H] 33[H] Function Enable Autostore Disable Autostore Store Operation
3874 PGM T12.2
* It should be noted, the high order addresses should remain stable during the operations. It should also be noted that these commands are not global, that is only one device on the module will be affected by each command operation.
Command Sequence Timing Limits Limits Symbol tSTO tSP tSPH
Note:
Parameter Store Time Command Write Pulse Width Inter Command Delay
Min. 50 55
Max. 5
Units ms ns ns
3874 PGM T01.1
All Write Command Sequence timings must conform to the standard write timing requirements.
Command Sequence
tSTO ADDRESS 555 2AAA 555
OE tSP CE
WE
NE tDS DATA IN AA tDH 55 CMD
3874 FHD F03.1
3
|
|
