· Replaces up to twenty 32 macro-cell CPLDs· Replaces up to one hundred 20-pin PAL® Packages· to 1153 Dedicated Flip-Flops· VQFP, TQFP, BGA, and PQFP Packages· Nonvolatile, User Programmable· Fully Tested Prior to Shipment· 5.0V and 3.3V Versions· Optimized for Logic Synthesis Methodologies· Low-power CMOS Technology
to 10,000 Gate Array Equivalent Gates (up to 25,000 equivalent PLD Gates)· Highly Predictable Performance with 100% Automatic Placement and Routing· 7.5 ns Clock-to-Output Times· to 250 MHz On-Chip Performance· to 228 User-Programmable I/O Pins· Four Fast, Low-Skew Clock Networks· More than 500 Macro Functions
Device Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages (40 gates) 20-Pin PAL Equivalent Packages (100 gates) Logic Modules S-Module C-Module Dedicated Flip-Flops1 User I/Os (maximum) Packages2 CPGA PLCC PQFP RQFP VQFP TQFP BGA CQFP Performance3 (maximum, worst-case commercial) Chip-to-Chip4 Accumulators (16-bit) Loadable Counter (16-bit) Prescaled Loadable Counters (16-bit) Datapath, Shift Registers Clock-to-Output (pad-to-pad) (by pin count)
Notes: 1. One flip-flop per S-Module, two flip-flops per I/O-Module. 2. See product plan on page 1-178 for package availability. 3. Based A1440B-3, A1460B-3, and A14100B-3. 4. Clock-to-Output + Setup
Actel's ACT 3 Accelerator Series of FPGAs offers the industry's fastest high-capacity programmable logic device. ACT 3 FPGAs offer a high perfomance, PCI compliant programmable solution capable of 250 MHz on-chip performance and 7.5 nanosecond clock-to-output, with capacities spanning from to 10,000 gate array equivalent gates. For further information regarding PCI compliance of ACT 3 devices, see "Accelerator Series FPGAs--ACT 3 PCI Compliant Family." The ACT 3 family builds on the proven two-module architecture consisting of combinatorial and sequential logic modules used in Actel's 3200DX and 1200XL families. In addition, the ACT 3 I/O modules contain registers which deliver 7.5 nanosecond clock-to-out times. The devices contain four clock distribution networks, including dedicated array and I/O clocks, supporting very fast synchronous and asynchronous designs. In addition, routed clocks can be used to drive high fanout signals such as flip-flop resets and output enables.
The ACT 3 family is supported by Actel's Designer Series Development System which offers automatic placement and routing (with automatic or fixed pin assignments), static timing anlaysis, user programming, and debug and diagnostic probe capabilities. The Designer Series is supported on the following platforms: 486/Pentium class PC's, Sun®, and HP®, workstations. The software provides CAE interfaces to Cadence, Mentor Graphics®, OrCADTM and Viewlogic®, design environments. Additional platforms are supported through Actel's Industry Alliance Program, including DATA I/O (ABEL FPGA) and MINC.
Chip-to-Chip Performance (Worst-Case Commercial) tCKHS 7.5 9.0 tTRACE 1.0 tINSU 1.8 1.3 Total 11.3 ns MHz 97 88
Application (Temperature Range) C = Commercial I = Industrial M = Military = MIL-STD-883 Package Lead Count Package Type PG = Ceramic Pin Grid Array PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flatpack RQ = Plastic Power Quad Flatpack VQ = Very Thin (1.0 mm) Quad Flatpack TQ = Thin (1.4 mm) Quad Flatpack CQ = Ceramic Quad Flatpack BG = Plastic Ball Grid Array Speed Grade Std = Standard Speed 1 = Approximately 15% faster than Standard 2 = Approximately 25% faster than Standard 3 = Approximately 35% faster than Standard Die Revision Part Number = 1500 Gates 1500 Gates (3.3V) 2500 Gates 2500 Gates (3.3V) 4000 Gates 4000 Gates (3.3V) 6000 Gates 6000 Gates (3.3V) 10000 Gates 10000 Gates (3.3V)