|Category||Microprocessors => Application Specific|
|Company||Advanced Hardware Architectures, Inc.|
|Datasheet||Download AHA3422 datasheet
1.0 Introduction. 1 1.1 Conventions, Notations and Definitions. 1 1.2 Features. 1 1.3 Functional Overview. 2 System Configuration. 3 2.1 Microprocessor Interface. 3 Functional Description. 5 3.1 Data Ports. 5 3.2 DMA Mode. 5 3.3 Pad Word Handling in Burst Mode. 8 3.4 DMA Request Signals and Status. 8 3.4.1 FIFO Threshold. 8 3.4.2 Request During an End-of-Record. 9 3.4.3 Request Status Bits. 9 3.5 Data Format. 9 3.6 Odd Byte Handling. 10 3.6.1 Input, Pad Bytes and Error Checking. 10 3.6.2 Output and Pad Bytes. 10 3.7 Video Interface. 10 3.7.1 Video Output. 10 3.8 Algorithm. 11 3.9 Decompression Engine. 11 3.10 Prearming. 11 3.11 Interrupts. 11 3.12 Duplex Printing. 12 3.13 Blank Bands. 12 3.14 Low Power Mode. 12 3.15 Test Mode. 12 4.0 Register Descriptions. 13 4.1 System Configuration 0, Address 0x00 - Read/Write. 15 4.2 System Configuration 1, Address 0x01 - Read/Write. 15 4.3 Input FIFO Thresholds, Address 0x02 - Read/Write. 16 4.4 Output FIFO Thresholds, Address 0x03 - Read/Write. 16 4.5 Decompression Ports Status, Address 0x05 - Read Only. 16 4.6 Port Control, Address 0x06 - Read/Write. 17 4.7 Interrupt Status/Control 0, Address 0x07 - Read/Write. 17 4.8 Interrupt Mask 0, Address 0x09 - Read/Write. 18 4.9 Version, Address 0x0A - Read Only. 18 4.10 Decompression Record Length, Address 0x0F - Read/Write. 18 4.11 Decompression Control, Address 0x18 - Read/Write. 19 4.12 Decompression Reserved, Address 0x3A - Read/Write. 19 4.13 Decompression Line Length, Address 0x1D - Read/Write. 20 4.14 Interrupt Status/Control 1, Address 0x27 - Read/Write. 20 4.15 Interrupt Mask 1, Address 0x29 - Read/Write. 20 4.16 Decompression Record Count, Address 0x2D - Read/Write. 20 4.17 Pattern, Address 0x35 - Read/Write. 21 4.18 Decompression Control Prearm, Address 0x38 - Read/Write. 21 4.19 Control, Address 0x3F - Read/Write. 21 5.0 Signal Descriptions. 22 5.1 Microprocessor Interface. 22 5.2 Data Interface. 23 5.3 Video Interface. 23
5.4 System Control. 24 6.0 Pinout. 7.0 DC Electrical Specifications. 27 7.1 Operating Conditions. 27 7.2 Absolute Maximum Stress Ratings. 8.0 AC Electrical Specifications. 28 9.0 Package Specifications. 34 10.0 Ordering Information. 35 10.1 Available Parts. 35 10.2 Part Numbering. 35 11.0 Related Technical Publications. 36 Appendix A: Additional Timing Diagrams for DMA Mode Transfers. 37 Appendix B: Sequential Register Table. 44
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