|Category||Microprocessors => Application Specific|
|Company||Advanced Hardware Architectures, Inc.|
|Datasheet||Download AHA3540 datasheet
1.0 Introduction. 1 1.1 Conventions, Notations and Definitions. 1 1.2 Features. 1 1.3 Applications. 1 1.4 Functional Description. 2 1.4.1 Port A and Port B Interfaces. 3 1.4.2 Data Expansion During Compression. 3 1.4.3 Multiple Records. 3 1.4.4 Byte Alignment. 3 2.0 Compression Operation. 4 2.1 Compression Pass Through. 4 2.2 Compression. 4 3.0 Decompression Operation. 5 3.1 Decompression Pass Through. 5 3.2 Decompression. 5 3.3 Decompression Output Disabled Mode. 5 4.0 Microprocessor Interface and Register Access. 5 4.1 Microprocessor Interface. 5 4.1.1 Interrupts. 5 4.1.2 Resets. 6 4.1.3 Port A Interface FIFO Access. 6 4.2 Register Access. 7 4.3 Pausing / Resume. 7 5.0 Port A and Port B Configuration. 7 6.0 Register Description. 8 6.1 Status 9 6.2 Status 10 6.3 Port A Configuration 11 6.4 Port A Configuration 11 6.5 Port B Configuration 11 6.6 Port B Configuration 12 6.7 Identification 12 6.8 Port A Polarity (APOL). 12 6.9 Port B Polarity (BPOL). 13 6.10 Port A Transfer Count 13 6.11 Record Count 14 6.12 Port B Compare Count 14 6.13 Port B Transfer Count 15 6.14 Port A FIFO Data Access 15 6.15 Compressed Bytes Processed 16 6.16 Port A FIFO Control (AFCT). 16 6.17 Error Status (ERRS). 17 6.18 Interrupt Status 17 6.19 Interrupt Status 18 6.20 Command (CMND). 19 6.21 Record Length 20 6.22 Data Disabled Count 20 6.23 Error Mask (EMSK). 21 6.24 Interrupt Mask 22 6.25 Interrupt Mask 22 7.0 Signal Descriptions. 23 7.1 Microprocessor Interface. 23
7.2 Port A Interface. 24 7.3 Port B Interface. 24 8.0 Pinout. 25 9.0 Electrical Specifications. 27 9.1 Absolute Maximum Ratings. 27 9.2 Recommended Operating Conditions. 9.3 DC Specifications. 27 10.0 Timing Specifications. 28 11.0 Packaging. 45 12.0 Ordering Information. 47 12.1 Available Parts. 47 12.2 Part Numbering. 47 13.0 AHA Related Technical Publications. 47 Appendix A:. Differences between the AHA3540 and IBM ALDC1-20S-LP48 Status and Interrupt Status Register Differences 48 Input/Output Differences 48
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