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Part: AAM29LV128MHH103EI
Category:
Memory
-> Flash
Description: 128 Megabit ( 8 M X 16-bit/16 M X 8-bit ) Mirrorbit 3.0 Volt-only Uniform Sector Flash Memory With Versatilei/o Control
Company: Advanced Micro Devices, Inc.
Datasheet: Download AAM29LV128MHH103EI datasheet File size : 132 kB
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Am29LV128MH/L
Data Sheet
July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Ple ase contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number 25270 Revision C
Amendment +2 Issue Date September 9, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
DATASHEET
Am29LV128MH/L
128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBitTM 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/OTM Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES Single power supply operation -- 3 volt read, erase, and program operations VersatileI/OTM control -- Device generates data output voltages and tolerates data input voltages on the CE# and DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V Manufactured on 0.23 µm MirrorBit process technology SecSiTM (Secured Silicon) Sector region -- 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence -- May be programmed and locked at the factory or by the customer Flexible sector architecture -- Two hundred fifty-six 32 Kword (64 Kbyte) sectors Compatibility with JEDEC standards -- Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection Minimum 100,000 erase cycle guarantee per sector 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS High performance -- 90 ns access time -- 25 ns page read times -- 0.5 s typical sector erase time -- 15 s typical effective write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word updates -- 4-word/8-byte page read buffer -- 16-word/32-byte write buffer Low power consumption (typical values at 3.0 V, 5 MHz) -- 13 mA typical active read current -- 50 mA typical erase/program current -- 1 µA typical standby mode current Package options -- 56-pin TSOP -- 64-ball Fortified BGA SOFTWARE & HARDWARE FEATURES Software features -- Program Suspend & Resume: read other sectors before programming operation is completed -- Erase Suspend & Resume: read/program other sectors before an erase operation is completed -- Data# polling & toggle bits provide status -- Unlock Bypass Program command reduces overall multiple-word or byte programming time -- CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices Hardware features -- Sector Group Protection: hardware-level method of preventing write operations within a sector group -- Temporar y Sector Group Unprotect: VID-level method of changing code in locked sector groups -- WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings -- Hardware reset input (RESET#) resets device -- Ready/Busy# output (RY/BY#) detects program or erase cycle completion
This Data Sheet states AMD's current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 25270 Rev: C Amendment/2 Issue Date: September 9, 2003
Refer to AMD's Website (www.amd.com) for the latest information.
DATASHEET
GENERAL DESCRIPTION
T h e Am29LV128MH/L is a 128 Mbit, 3.0 volt single p o w e r supply flash memory devices organized as 8,388,608 words or 16,777,216 bytes. The device has a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in standard EPROM programmers. An access time of 90, 100, 110, or 120 ns is available. N o te that each access time has a specific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in the Product Selector Guide and the Orderi n g Information sections. The device is offered in a 56-pin TSOP, 64-ball Fortified BGA. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. E a c h device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V C C input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with t h e JEDEC single-power-supply Flash standard. Co mman ds are written to the device using standard micro proce ssor write timing. Write cycles also intern a l ly latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase opera tio n has begun, the host system need only poll the D Q 7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. The VersatileI/OTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os to the same voltage level that is asserted on the VIO pin. Refer to the Ordering Information section for valid VIO options. H a rdw a re data protection measures include a low V C C detector that automatically inhibits write operat io n s during power transitions. The hardware sector gro u p protection feature disables both program and erase operations in any combination of sector groups of memory. This can be achieved in-system or via programming equipment. T h e Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given se cto r to read or program any other sector and then c o m p l e t e the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then rea dy for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. T h e device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. T h e SecSiTM (Secured Silicon) Sector provides a 128 -word/256-byte area for code or data that can be per manently protected. Once this sector is protected, no further changes within the sector can occur. T h e Write Protect (WP#/ACC) feature protects the first or last sector by asserting a logic low on the WP# pin. A M D MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.
RELATED DOCUMENTS
Fo r a comprehensive information on MirrorBit products, including migration information, data sheets, app l i c a t i o n notes, and software drivers, please see w w w. a m d . c o m F la s h MemoryProduct InformationMirrorBitFlash InformationTechnical Documentation. The following is a partial list of documents closely related to this product: MirrorBitTM Flash Memory Write Buffer Programming and Page Buffer Read I m p le m e n t i n g a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices Migrating from Single-byte to Three-byte Device IDs Am29LV256M, 256 Mbit MirrorBit Flash device (in 64-ball, 18 x 12 mm Fortified BGA package)
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Am29LV128MH/L
September 9, 2003
DATASHEET
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 4 4 5 7 7 8 9 Erase Suspend/Erase Resume Commands ... 33 Command Definitions .... 34
Table 10. Command Definitions (x16 Mode, BYTE# = VIH) .. 34 Table 11. Command Definitions (x8 Mode, BYTE# = VIL) ..... 35
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 36 DQ7: Data# Polling ........ 36
Figure 8. Data# Polling Algorithm ........ 36
Table 1. Device Bus Operations ....... 9
Word/Byte Configuration .......... 9 VersatileIOTM (VIO) Control ....... 9 Requirements for Reading Array Data .. 10
Page Mode Read ..........10
RY/BY#: Ready/Busy# ... 37 DQ6: Toggle Bit I ........... 37
Figure 9. Toggle Bit Algorithm ........ 38
Writing Commands/Command Sequences .... 10
Write Buffer ....10 Accelerated Program Operation ......10 Autoselect Functions .....10
DQ2: Toggle Bit II .......... 38 Reading Toggle Bits DQ6/DQ2 ..... 38 DQ5: Exceeded Timing Limits ...... 39 DQ3: Sector Erase Timer ....... 39 DQ1: Write-to-Buffer Abort ..... 39
Table 12. Write Operation Status......... 40
Standby Mode ...... 10 Automatic Sleep Mode .. 11 RESET#: Hardware Reset Pin ..... 11 Output Disable Mode ..... 11
Table 2. Sector Address Table........ 12
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 41
Figure 10. Maximum Negative Overshoot Waveform .......... 41 Figure 11. Maximum Positive Overshoot Waveform ............ 41
Autoselect Mode ............ 18
Table 3. Autoselect Codes, (High Voltage Method) ..... 18
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 41 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. Test Setup ........... 43 Table 13. Test Specifications ......... 43
Sector Group Protection and Unprotection ..... 19
Table 4. Sector Group Protection/Unprotection Address Table ..... 19
Key to Switching Waveforms. . . . . . . . . . . . . . . . 43
Figure 13. Input Waveforms and Measurement Levels ........ 43
Write Protect (WP#) ....... 20 Temporary Sector Group Unprotect ...... 20
Figure 1. Temporary Sector Group Unprotect Operation .......20 Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...21
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44 Read-Only Operations .. 44
Figure 14. Read Operation Timings ..... 44 Figure 15. Page Read Timings ...... 45
SecSi (Secured Silicon) Sector Flash Memory Region .......... 22
Table 5. SecSi Sector Contents ...... 22 Figure 3. SecSi Sector Protect Verify ....23
Hardware Reset (RESET#) .... 46
Figure 16. Reset Timings ...... 46
Hardware Data Protection ...... 23
Low VCC Write Inhibit ............23 Write Pulse "Glitch" Protection ........23 Logical Inhibit ..........23 Power-Up Write Inhibit ...........23
Erase and Program Operations .... 47
Figure 17. Reset Timings ...... 48 Figure 18. Program Operation Timings ......... 49 Figure 19. Accelerated Program Timing Diagram .. 49 Figure 20. Chip/Sector Erase Operation Timings .. 50 Figure 21. Data# Polling Timings (During Embedded Algorithms) . 51 Figure 22. Toggle Bit Timings (During Embedded Algorithms) ...... 52 Figure 23. DQ2 vs. DQ6 ........ 52
Common Flash Memory Interface (CFI) . . . . . . . 23
Table 6. CFI Query Identification String .........24 Table 7. System Interface String..... 24 Table 8. Device Geometry Definition ....25 Table 9. Primary Vendor-Specific Extended Query ......26
Temporary Sector Group Unprotect ...... 53
Figure 24. Temporary Sector Group Unprotect Timing Diagram ... 53 Figure 25. Sector Group Protect and Unprotect Timing Diagram .. 54
Command Definitions . . . . . . . . . . . . . . . . . . . . . 27 Reading Array Data ....... 27 Reset Command ............ 27 Autoselect Command Sequence ........... 27 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 28 Word/Byte Program Command Sequence ..... 28
Unlock Bypass Command Sequence ....28 Write Buffer Programming ......28 Accelerated Program ....29 Figure 4. Write Buffer Programming Operation .......30 Figure 5. Program Operation ..........31
Alternate CE# Controlled Erase and Program Operations ..... 55
Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings ........ 56
Program Suspend/Program Resume Command Sequence ... 31
Figure 6. Program Suspend/Program Resume .......32
Chip Erase Command Sequence .......... 32 Sector Erase Command Sequence ....... 32
Figure 7. Erase Operation ......33
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 56 Erase And Programming Performance. . . . . . . . 57 TSOP Pin and BGA Package Capacitance . . . . . 58 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 59 TS056/TSR056--56-Pin Standard/Reverse Thin Small Outline Package (TSOP) ............ 59 LAA064--64-Ball Fortified Ball Grid Array 13 x 11 mm Package ..... 60 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61
September 9, 2003
Am29LV128MH/L
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