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Part: AM27C04-90PE
Category:
Memory
-> EPROM
-> 8 Mb
Description: 4 Megabit ( 512 K X 8-bit ) CMOS EPROM
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM27C04-90PE datasheet File size : 679 kB
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Datasheet text preview:
FINAL
Am27C040
4 Megabit (512 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s Fast access time -- Available in speed options as fast as 90 ns s Low power consumption -- <10 µA typical CMOS standby current s JEDEC-approved pinout -- Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs -- Easy upgrade from 28-pin JEDEC EPROMs s Single +5 V power supply s ±10% power supply tolerance standard s 100% FlashriteTM programming -- Typical programming time of 1 minute s Latch-up protected to 100 mA from 1 V to VCC + 1 V s High noise immunity s Compact 32-pin DIP, PDIP, PLCC packages
GENERAL DESCRIPTION
T h e Am27C040 is a 4 Mbit ultraviolet erasable programmable read-only memory. It is organized as 512K bytes, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The device is available in windowed ceramic DIP packages and plastic one-time programmable (OTP) packages. Data can be typically accessed in less than 90 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor system. A M D 's CMOS process technology provides high sp ee d , low power, and high noise immunity. Typical p ower consumption is only 100 mW in active mode, and 50 µW in standby mode. All signals are TTL levels, including programming sign a l s . Bit locations may be programmed singly, in b l o ck s , or at random. The device supports AMD's Flashr ite programming algorithm (100 µs pulses) resulting in typical programming time of 1 minute.
BLOCK DIAGRAM
VCC VSS VPP OE# Output Enable Chip Enable and Prog Logic Y Decoder A0A18 Address Inputs Data Outputs DQ0DQ7
Output Buffers
CE#/PGM#
Y Gating
X Decoder
4,194,304-Bit Cell Matrix
14971G-1
Publication# 14971 Rev: G Amendment/0 Issue Date: May 1998
FINAL
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options (VCC = 5.0 V ± 10%) Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns) -90 90 90 40 Am27C040 -120 120 120 50 -150 150 150 65 -200 200 200 75
CONNECTION DIAGRAMS Top View
DI P
A12 A15 A16 V PP
P L CC
V CC A18 A17 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A18 A17 A14 A13 A8 A9 A11 OE# (G#) A10 CE# (E#)/PGM# (P#) DQ7 DQ6 DQ5 DQ4 DQ3 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
4
3
2 1 32 31 30 A14 A13 A8 A9 A11 OE# (G#) A10 CE# (E#)/PGM# (P#) DQ7
14971G-3
14971G-2
Notes: 1. JEDEC nomenclature is in parenthesis. 2. The 32-pin DIP to 32-pin PLCC configuration varies from the JEDEC 28-pin DIP to 32-pin PLCC configuration.
PIN DESIGNATIONS
A0A18 = Address Inputs Chip Enable/Program Enable Input Data Inputs/Outputs Output Enable Input VCC Supply Voltage Program Voltage Input GroundLogic Symbol CE# (E#)/PGM# (P#)= DQ0DQ7 OE# (G#) VCC VPP VSS = = = = =
LOGIC SYMBOL
19 A0A18 DQ0DQ7 CE# (E#)/PGM#(P#) OE# (G#) 8
14971E-4
2
Am 2 7 C 0 4 0
FINAL
ORDERING INFORMATION UV EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of:
AM27C040
-90
D
C OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (40°C to +85°C) E = Extended (55°C to +125°C) PACKAGE TYPE D = 32-Pin Ceramic DIP (CDV032) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION Am27C040 4 Megabit (512K x 8-Bit) CMOS UV EPROM
Valid Combinations Valid Combinations AM27C040-90 AM27C040-120 DC, DCB, DI, DIB, DE, DEB AM27C040-150 AM27C040-200 Valid Combinations list configurations planned to be suppor ted in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am27C040
3
FINAL
ORDERING INFORMATION OTP EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of:
AM27C040
-90
J
C OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (40°C to +85°C) E = Extended (55°C to 125°C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION Am27C040 4 Megabit (512K x 8-Bit) CMOS OTP EPROM
Valid Combinations AM27C040-90 AM27C040-120 PC, PI, JC, JI AM27C040-150 AM27C040-200
Valid Combinations Valid Combinations list configurations planned to be suppor ted in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4
Am 2 7 C 0 4 0
FINAL
FUNCTIONAL DESCRIPTION Device Erasure
I n order to clear all locations of their programmed contents, the device must be exposed to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase the device. This dosage can be obtained by exposure to an ultraviolet lamp -- wavelength of 2537 Å -- with intensity of 12,000 µW/cm2 for 15 to 20 minutes. The device should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000 Å, such as fluorescent light and sunlight. Although the erasure process happens over a much longer time period, exp o s u r e to any light source should be prevented for maximum system reliability. Simply cover the package window with an opaque label or substance.
that particular device. A high-level CE#/PGM# input inhibits the other devices from being programmed.
Program Verify
A verification should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE# at VIL, CE#/ PGM# at VIH, and VPP between 12.5 V and 13.0 V.
Auto Select Mode
The autoselect mode provides manufacturer and device identification through identifier codes on DQ0 DQ7. This mode is primarily intended for programming equipment to automatically match a device to be program me d with its corresponding programming algor i t h m . This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the device. To activate this mode, the programming equipment must force VH on address line A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH (that is, changing the address from 00h to 01h). All other address lines must be held at VIL during the autoselect mode. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. Both codes have odd parity, with DQ7 as the parity bit.
Device Programming
Upon delivery, or after each erasure, the device has all of its bits in the "ONE", or HIGH state. "ZEROs" are loaded into the device through the programming proc e d u re . T h e programming mode is entered when 12.75 V ± 0.25 V is applied to the VPP pin, CE#/PGM# is at VIL and OE# is at VIH . For programming, the data to be programmed is applied 8 bits in parallel to the data output pins. The flowchart in the EPROM Products Data Book, Programming section (Section 5, Figure 5-1) shows AMD's Flashrite algorithm. The Flashrite algorithm reduces programming time by using a 100 µs programming pulse and by giving each address only as many pulses to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process is repeated while sequencing through each address of the device. This part of the algorithm is done at VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memor y is verified at VCC = VPP = 5.25 V. Please refer to the EPROM Products Data Book, Section 5 for the programming flow chart and characteristics.
Read Mode
To obtain data at the device outputs, Chip Enable (CE#/ PGM#) and Output Enable (OE#) must be driven low. CE#/PGM# controls the power to the device and is typically used to select the device. OE# enables the device to output data, independent of device selection. Addresses must be stable for at least tACCtOE. Refer to th e Switching Waveforms section for the timing diagram.
Standby Mode
T h e device enters the CMOS standby mode when CE#/PGM# is at VCC ± 0.3 V. Maximum VCC current is reduced to 100 µA. The device enters the TTL-standby mode when CE#/PGM# is at VIH. Maximum VCC curr e n t is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-impedance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a two-line control function is provided to allow for: s Low memory power dissipation, and s Assurance that output bus contention will not occur CE#/PGM# should be decoded and used as the primary device-selecting function, while OE# be made a
Program Inhibit
Programming different data to multiple devices in parallel is easily accomplished. Except for CE#/PGM#, all l i ke inputs of the devices may be common. A TTL low-level program pulse applied to one device's CE#/ PGM# input with VPP = 12.75 V ± 0.25 V will program
Am27C040
5
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