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Part: AM28F256-75C
Category:
Memory
-> Flash
Description:
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM28F256-75C datasheet File size : 427 kB
Request For quote: Find where to buy AM28F256-75C
Datasheet text preview:
FINAL
Am28F256
256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s High performance -- 70 ns maximum access time s CMOS Low power consumption -- 30 mA maximum active current -- 100 µA maximum standby current -- No data retention power consumption s Compatible with JEDEC-standard byte-wide 32-Pin EPROM pinouts -- 32-pin PDIP -- 32-pin PLCC -- 32-pin TSOP s 10,000 write/erase cycles minimum s Write and erase voltage 12.0 V ±5% s Latch -up protected to 100 mA from 1 V to V CC +1 V s Flasherase Electrical Bulk Chip-Erase -- One second typical chip-erase s Flashrite Programming -- 10 µs typical byte-program -- 0.5 second typical chip program s Comm and register architecture for microp rocessor/microco ntro ller compatible write interface s On -chip address and data latches s Advanced CMOS flash memory technology -- Low cost single transistor memory cell s Automatic write/erase pulse stop timer
GENERAL DESCRIPTION
The Am28F256 is a 256 K Flash memory organized as 32 Kbytes of 8 bits each. AMD's Flash memories offer t h e most cost-effective and reliable read/write nonvo l a t i l e random access memory. The Am28F256 is packaged in 32-pin PDIP PLCC, and TSOP versions. It , is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F256 is erased when shipped from the factory. The standard Am28F256 offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, th e Am28F256 has separate chip enable (CE#) and output enable (OE#) controls. AMD's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am2 8F25 6 uses a command register to manage this f u n c t i o n a l i t y, while maintaining a standard JEDEC Flash Standard 32-pin pinout. The command register a l l ow s for 100% TTL level control inputs and fixed power supply levels during erase and programming. A M D 's Flash technology reliably stores memor y contents even after 10,000 erase and program cycles.
P ublicatio n# 11560 Rev: G A men dme nt/+2 Issue Date: January 1998
Th e AMD cell is designed to optimize the erase and pro gramm ing mechanisms. In addition, the combinat i o n of advanced tunnel oxide processing and low i n t e r n a l electric fields for erase and programming opera tions produces reliable cycling. The Am28F256 uses a 12.0V ± 5% VPP high voltage input to perform the Flasherase and Flashrite algorithms. The highest degree of latch-up protection is achieved w i t h AMD's proprietar y non-epi process. Latch-up protection is provided for stresses up to 100 milliamps on address and data pins from 1 V to V CC +1 V. T h e Am28F256 is byte programmable using 10 µs p r o g r a m m i n g pulses in accordance with AMD's F l a s h r ite programming algorithm. The typical room temperature programming time of the Am28F256 is a ha l f a second. The entire chip is bulk erased using 10 ms erase pulses according to AMD's Flasherase a l r o g i th m . Typical erasure at room temperature is accomplished in less than one second. The windowed package and the 15-20 minutes required for EPROM erasure using ultra-violet light are eliminated.
Commands are written to the command register using stand ard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase o p e r a t i o n s . For system design simplification, the Am28F256 is designed to support either WE# or CE# c o n tr o l l e d writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occurs first. To simplify the fol-
lowing discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal. AM D's Flash technology combines years of EPROM and EEPROM experience to produce the highest levels o f quality, reliability, and cost effectiveness. The Am 28 F2 56 electrically erases all bits simultaneously u s i n g Fowler-Nordheim tunneling. The bytes are p ro g ra m m e d one byte at a time using the EPROM programming mechanism of hot electron injection.
BLOCK DIAGRAM
DQ0DQ7 VC C VS S VP P Erase Voltage Switch S ta te Control To Array Input/Output Buffers
W E#
Command Register CE# OE#
Program Voltage Switch
Chip Enable Output Enable Logic Data Latch
Low V CC Detector Program/Erase Pulse Timer A0A14
Y-Decoder
Y-Gating
Address L a tc h
X-Decoder
262,144 Bit Cell Matrix
11560F -1
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options (VCC = 5.0 V ± 10%) Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns) -70 70 70 35 -90 90 90 35 Am28F256 -120 120 120 50 -150 150 150 55 -200 200 200 55
2
A m28F256
CONNECTION DIAGRAMS PDIP
V PP NC NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 V SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC
P L CC
WE# (W#) NC
NC A14 A13 A8 A9 A11 OE# (G#) A10 CE# (E#) DQ7 DQ6 DQ5 DQ4 DQ3
43 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
2
1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE# (G#) A10 CE# (E#) DQ7
14 15 16 17 18 19 20 VSS DQ3 DQ1 DQ2 DQ4 DQ5 DQ6
VCC
A12 NC
V PP
WE# (W#)
NC
11560F -2
11560F-3
Note: Pin 1 is marked for orientation.
Am28F256
3
CONNECTION DIAGRAMS (continued)
A11 A9 A8 A13 A14 NC W E# VCC V PP NC NC A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# D7 D6 D5 D4 D3 V SS D2 D1 D0 A0 A1 A2 A3
32-Pin TSOP--Standard Pinout
OE# A10 CE# D7 D6 D5 D4 D3 V SS D2 D1 D0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 A14 NC WE# VCC V PP NC NC A12 A7 A6 A5 A4
11560G-4
32-Pin TSOP--Reverse Pinout
LOGIC SYMBOL
15 A0A14 DQ0DQ7 8
CE# (E#) OE# (G#) WE# (W#)
11560F-5
4
A m28F256
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of:
AM28F256
-70
J
C
B OPTIONAL PROCESSING Blank = Standard Processing B = Bur n-In Contact an AMD representative for more information. TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (40°C to +85°C) E = Extended (55°C to +125°C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION Am28F256 256 Kilobit (32 K x 8-Bit) CMOS Flash Memory
Valid Combinations AM28F256-70 AM28F256-90 AM28F256-120 AM28F256-150 AM28F256-200 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE
Valid Combinations Va li d Combinations list configurations planned to be suppor ted in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am28F256
5
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