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Part: Am29DL16xCB
Category:
Description:
Company: Advanced Micro Devices, Inc.
Datasheet: Download Am29DL16xCB datasheet File size : 233 kB
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PRELIMINARY
Am29DL16xC
16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES s Simultaneous Read/Write operations -- Data can be continuously read from one bank while executing erase/program functions in other bank -- Zero latency between read and write operations s Multiple bank architectures -- Three devices available with different bank sizes (refer to Table 2) s Secured Silicon (SecSi) Sector: Extra 64 KByte sector -- Factor y locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data -- Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed s Zero Power Operation -- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero s Package options -- 48-ball FBGA -- 56-pin SSOP -- 48-pin TSOP s Top or bottom boot block s Manufactured on 0.32 µm process technology s Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS s High performance -- Access time as fast 70 ns -- Program time: 7 µs/word typical utilizing Accelerate function s Ultra low power consumption (typical values) -- 2 mA active read current at 1 MHz -- 10 mA active read current at 5 MHz -- 200 nA in standby or automatic sleep mode s Minimum 1 million write cycles guaranteed per sector s 20 Year data retention at 125°C -- Reliable operation for the life of the system SOFTWARE FEATURES s Data Management Software (DMS) -- AMD-supplied software manages data programming and erasing, enabling EEPROM emulation -- Eases sector erase limitations s Supports Common Flash Memory Interface (CFI) s Erase Suspend/Erase Resume -- Suspends erase operations to allow programming in same bank s Data# Polling and Toggle Bits -- Provides a software method of detecting the status of program or erase cycles s Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES s Any combination of sectors can be erased s Ready/Busy# output (RY/BY#) -- Hardware method for detecting program or erase cycle completion s Hardware reset pin (RESET#) -- Hardware method of resetting the internal state machine to reading array data s WP#/ACC input pin -- Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status -- Acceleration (ACC) function accelerates program timing s Sector protection -- Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector -- Temporar y Sector Unprotect allows changing data in protected sectors in-system
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 21533 Rev: C Amendment/+5 Issue Date: October 18, 1999
Refer to AMD's Website (www.amd.com) for the latest information.
PRELIMINARY
GENERAL DESCRIPTION
Th e Am29DL16xC family consists of 16 megabit, 3.0 volt-only flash memory devices, organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. Word mode data appears on DQ0DQ15; byte mode data appears on DQ0DQ7. The device is designed to b e programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70, 80, 90, or 120 ns. The devices are offered in 56-pin SSOP, 48-pin TSOP, and 48-ball FBGA packages. Standard control pins--chip enable (CE#), write enable (WE#), a n d output enable (OE#)--control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supp l y for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, a s opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs t o state which piece of data is to be updated, and where the updated data is located in the system. This i s a n a d va n t a g e c o m p a r e d t o s y s te m s w h e r e user-wr itten software must keep track of the old data l o cation , status, logical to physical translation of the d a ta onto the Flash memory device (or memory device s), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memor y by calling one of only six functions. AMD prov i d e s this software to simplify system design and software integration efforts. The device offers complete compatibility with the J E D E C single-power-supply Flash command set s t a n d a rd . Commands are written to the command register using standard microprocessor write timings. R e a d i n g data out of the device is similar to reading from other Flash or EPROM devices. T h e host system can detect whether a program or erase operation is complete by using the device stat u s bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. H a rdw a re data protection measures include a low V C C detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memo r y. T h i s c a n b e a c h i e v e d i n - s y s t e m o r v i a programming equipment. T h e device offers two power-saving features. When addresses have been stable for a specified amount of t im e, the device enters the automatic sleep mode. T h e system can also place the device into the s t a n d by mode. Power consumption is greatly reduced in both modes.
Simultaneous Read/Write Operations with Zero Latency
Th e Simultaneous Read/Write architecture provides s i m u l t a n e o u s operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to prog r a m or erase in one bank, then immediately and simultaneously read from the other bank, with zero lat en cy. This releases the system from waiting for the completion of program or erase operations. T h e Am29DL16xC device family uses multiple bank architectures to provide flexibility for different applicat io n s. Three devices are available with the following bank sizes:
Device D L1 62 D L1 63 D L1 64 Bank 1 2 Mb 4 Mb 8 Mb Bank 2 14 Mb 12 Mb 8 Mb
Am29DL16xC Features
T h e Secured Silicon (SecSi) Sector is an extra 64 K b i t sector capable of being permanently locked by AMD or customers. The SecSi Sector Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Fa c t o r y locked parts provide several options. The S e c S i Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (prog ra m m e d through AMD's ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi S ecto r as bonus space, reading and writing like any
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Am29DL16xC
PRELIMINARY
PRODUCT SELECTOR GUIDE
Part Number Speed Option Max Access Time (ns) CE# Access (ns) OE# Access (ns) Standard Voltage Range: VCC = 2.73.6 V 70, 70R 70 70 30 Am29DL16xC 80 80 80 30 90 90 90 40 120 120 120 50
BLOCK DIAGRAM
VCC VSS OE# BYTE#
Y-Decoder
A0A19
Upper Bank Address
Upper Bank
Latches and Control Logic
RY/BY#
A0A19 RESET# WE# CE# BYTE# WP#/ACC DQ0DQ15 STATE CONTROL & COMMAND REGISTER
X-Decoder
Status DQ0DQ15 Control
A0A19
X-Decoder
Lower Bank
A0A19
Lower Bank Address
Latches and Control Logic
Y-Decoder
DQ0DQ15
DQ0DQ15
A0A19
21533C-1
Am29DL16xC
3
PRELIMINARY
CONNECTION DIAGRAMS
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-Pin Standard TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
21533C-2
NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC NC NC A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56-Pin SSOP
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
RESET# WE# NC A19 A8 A9 A10 A11 A12 A13 A14 A15 NC NC NC NC A16 BTYE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
4
Am29DL16xC
PRELIMINARY
CONNECTION DIAGRAMS
48-Ball FBGA Top View, Balls Facing Down
A6 A13 A5 A9 A4 WE# A3
B6 A12 B5 A8 B4 RESET# B3
C6 A14 C5 A10 C4 NC C3 A18 C2 A6 C1 A2
D6 A15 D5 A11 D4 A19 D3 NC D2 A5 D1 A1
E6 A16 E5 DQ7 E4 DQ5 E3 DQ2 E2 DQ0 E1 A0
F6
G6
H6 VSS H5 DQ6 H4 DQ4 H3 DQ3 H2 DQ1 H1 VSS
BYTE# DQ15/A-1 F5 DQ14 F4 DQ12 F3 DQ10 F2 DQ8 F1 CE# G5 DQ13 G4 VCC G3 DQ11 G2 DQ9 G1 OE#
RY/BY# WP#/ACC A2 A7 A1 A3 B2 A17 B1 A4
21533C-4
Special Handling Instructions for FBGA Package
S pecia l handling is required for Flash Memory products in FBGA packages.
F l a s h memory devices in FBGA packages may be d amaged if exposed to ultrasonic cleaning methods. T h e package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
Am29DL16xC
5
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