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Part: AM29F010-45
Category:
Memory
-> Flash
Description:
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29F010-45 datasheet File size : 1483 kB
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Datasheet text preview:
FINAL
Am29F010
1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation -- 5.0 V ± 10% for read, erase, and program operations -- Simplifies system-level power requirements s High performance -- 45 ns maximum access time s Low power consumption -- 30 mA max active read current -- 50 mA max program/erase current -- <25 µA typical standby current s Flexible sector architecture -- Eight uniform sectors -- Any combination of sectors can be erased -- Suppor ts full chip erase s Sector protection -- Hardware-based feature that disables/reenables program and erase operations in any combination of sectors -- Sector protection/unprotection can be implemented using standard PROM programming equipment s Embedded Algorithms -- Embedded Erase algorithm automatically pre-programs and erases the chip or any combination of designated sector -- Embedded Program algorithm automatically programs and verifies data at specified address s Minimum 100,000 program/erase cycles guaranteed s Package options -- 32-pin PLCC -- 32-pin TSOP -- 32-pin PDIP s Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply flash -- Superior inadvertent write protection s Data# Polling and Toggle Bits -- Provides a software method of detecting program or erase cycle completion
Publication# 16736 Rev: G Amendment/+3 Is sue Date: July 1998
GENERAL DESCRIPTION
The Am29F010 is a 1 Mbit, 5.0 Volt-only Flash memory organized as 131,072 bytes. The Am29F010 is offered in 32-pin PLCC, TSOP, and PDIP packages. The bytewide data appears on DQ0-DQ7. The device is designed to be programmed in-system with the standard system 5.0 Volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed or erased in standard EPROM programmers. The standard device offers access times of 45, 55, 70, 90, and 120 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus conten tion the device has separate chip enable (CE#), write enable (WE#) and output enable (OE) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally genera t e d and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also inter nally latch addresses and data needed for the programming and erase operations. Reading data out of th e device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This invokes the Embedded Program algorithm--an internal algorithm that automatic a l ly times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This invokes the Embedded Erase a lgo r it h m-- a n internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. T h e host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is erased when shipped from the factory. The hardware data protection measures include a low VCC detector automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory, and is implemented using standard EPROM programmers. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the h i g h e s t l e v e l s o f qu a l i t y, r e l i a b i l i t y, a n d c o s t effectiven ess. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
2
Am29F010
PRODUCT SELECTOR GUIDE
Family Part Number Speed Option VCC = 5.0 V ± 5% VCC = 5.0 V ± 10% 45 45 25 -45 -55 (P) -55 (J, E, F) 55 55 30 -70 70 70 30 -90 90 90 35 -120 120 120 50 Am29F010
Max Access Time (ns) CE# Access (ns) OE# Access (ns)
Note: See the AC Characteristics section for full specifications.
BLOCK DIAGRAM
DQ0DQ7
VCC VSS
Erase Voltage Generator
Input/Output Buffers
WE#
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A16
16736G-1
Am29F010
3
CONNECTION DIAGRAMS
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 VCC WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
16736G-2 16736G-3
432 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
1 32 31 30 29 28 27 26 A14 A13 A8 A9 A11 OE# A10 CE# DQ7
PDIP 25 24
23 22 21 20 19 18 17
PLCC
WE# NC 25 24 23 22 21 DQ5 DQ6
A16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
14 15 16 17 18 19 20 VSS DQ3 DQ1 DQ2 DQ4
A11 A9 A8 A13 A14 NC WE# VCC NC A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standard TSOP
VCC
A12 A15
NC
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
16736G-4
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Reverse TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 A14 NC WE# VCC NC A16 A15 A12 A7 A6 A5 A4
16736G -5
4
Am29F010
PIN CONFIGURATION
A0A16 = 17 Addresses DQ0DQ7 = 8 Data Inputs/Outputs
LOGIC SYMBOL
17
CE# OE# WE# VCC
= Chip Enable = Output Enable = Write Enable = +5.0 Volt Single Power Supply (See Product Selector Guide for speed options and voltage supply tolerances) = Device Ground = Pin Not Connected Internally
A0A16 DQ0DQ7 CE# OE# WE #
8
VS S NC
16736G-6
Am29F010
5
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