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Part: AM29F016D-90SIB
Category:
Memory
-> Flash
Description: 16 Megabit ( 2 M X 8-bit ) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29F016D-90SIB datasheet File size : 1483 kB
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Am29F016D
Data Sheet
July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number 21444 Revision E
Amendment +2 Issue Date March 23, 2001
Am29F016D
16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 V ± 10%, single power supply operation -- Minimizes system level power requirements s Manufactured on 0.23 µm process technology -- Compatible with 0.5 µm Am29F016 and 0.32 µm Am29F016B devices s High performance -- Access times as fast as 70 ns s Low power consumption -- 25 mA typical active read current -- 30 mA typical program/erase current -- 1 µA typical standby current (standard access time to active mode) s Flexible sector architecture -- 32 uniform sectors of 64 Kbytes each -- Any combination of sectors can be erased -- Suppor ts full chip erase -- Group sector protection: A hardware method of locking sector groups to prevent any program or erase operations within that sector group Temporary Sector Group Unprotect allows code changes in previously locked sectors s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies bytes at specified addresses s Unlock Bypass Program Command -- Reduces overall programming time when issuing multiple program command sequences s Minimum 1,000,000 program/erase cycles per sector guaranteed s 20-year data retention at 125°C -- Reliable operation for the life of the system s Package options -- 48-pin and 40-pin TSOP -- 44-pin SO -- Known Good Die (KGD) (see publication number 21551) s Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply Flash standard -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase cycle completion s Ready/Busy# output (RY/BY#) -- Provides a hardware method for detecting program or erase cycle completion s Erase Suspend/Erase Resume -- Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation s Hardware reset pin (RESET#) -- Resets internal state machine to the read mode
This Data Sheet states AMD's current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21444 Rev: E Amendment/+2 Issue Date: March 23, 2001
GENERAL DESCRIPTION
The Am29F016D is a 16 Mbit, 5.0 volt-only Flash memor y organized as 2,097,152 bytes. The 8 bits of data appear on DQ0DQ7. The Am29F016D is offered in 48-pin TSOP, 40-pin TSOP, and 44-pin SO packages. The device is also available in Known Good Die (KGD) form. For more information, refer to publication number 2 1 5 5 1 . This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase o p e ra t io n s. The device can also be programmed in standard EPROM programmers. This device is manufactured using AMD's 0.23 µm process technology, and offers all the features and benefits of the Am29F016, which was manufactured using 0.5 µm process technology. The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally genera t e d and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents ser ve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase a lg o r i t h m -- a n internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memor y. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. T h e system can place the device into the standby m o d e . Power consumption is greatly reduced in t h i s mode. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a s e c t o r simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
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Am 2 9 F 0 1 6 D
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 4 4 5 7 7 8 9 DQ3: Sector Erase Timer ....... 23
Figure 5. Toggle Bit Algorithm........ 23 Table 10. Write Operation Status......... 24
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 25
Figure 6. Maximum Negative Overshoot Waveform .... 25 Figure 7. Maximum Positive Overshoot Waveform ...... 25
Table 1. Am29F016D Device Bus Operations .......... 9
Requirements for Reading Array Data .... 9 Writing Commands/Command Sequences ...... 9 Program and Erase Operation Status ... 10 Standby Mode ...... 10 RESET#: Hardware Reset Pin ..... 10 Output Disable Mode..... 10
Table 2. Sector Address Table........ 11
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26 TTL/NMOS Compatible .......... 26 CMOS Compatible......... 26 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. Test Setup.... 27 Table 11. Test Specifications ......... 27
Autoselect Mode............ 12
Table 3. Am29F016D Autoselect Codes (High Voltage Method).... 12
Key to Switching Waveforms. . . . . . . . . . . . . . . . 27 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28 Read-only Operations.... 28
Figure 9. Read Operation Timings ....... 28 Figure 10. RESET# Timings .......... 29
Sector Group Protection/Unprotection... 12
Table 4. Sector Group Addresses......... 12
Erase/Program Operations ..... 30
Figure 11. Program Operation Timings......... Figure 12. Chip/Sector Erase Operation Timings .. Figure 13. Data# Polling Timings (During Embedded Algorithms). Figure 14. Toggle Bit Timings (During Embedded Algorithms)...... Figure 15. DQ2 vs. DQ6........ Figure 16. Temporary Sector Group Unprotect Timings ....... 31 32 33 33 34 34
Temporary Sector Group Unprotect ...... 12
Figure 1. Temporary Sector Group Unprotect Operation....... 13
Hardware Data Protection ...... 13
Low VCC Write Inhibit .... 13 Write Pulse "Glitch" Protection ........ 13 Logical Inhibit .......... 13 Power-Up Write Inhibit ........... 13
Erase and Program Operations .... 35
Alternate CE# Controlled Writes .... 35 Figure 17. Alternate CE# Controlled Write Operation Timings ...... 36
Common Flash Memory Interface (CFI) . . . . . . . 14
Table 5. CFI Query Identification String ......... 14 Table 6. System Interface String..... 14 Table 7. Device Geometry Definition .... 15 Table 8. Primary Vendor-Specific Extended Query ...... 15
Command Definitions . . . . . . . . . . . . . . . . . . . . . 16 Reading Array Data ....... 16 Reset Command............ 16 Autoselect Command Sequence ........... 16 Byte Program Command Sequence...... 16
Unlock Bypass Command Sequence.... 17 Figure 2. Program Operation .......... 17
Chip Erase Command Sequence .......... 17 Sector Erase Command Sequence ....... 18 Erase Suspend/Erase Resume Commands... 18
Figure 3. Erase Operation...... 19
Command Definitions .... 20
Table 9. Am29F016D Command Definitions.. 20
Write Operation Status . . . . . . . . . . . . . . . . . . . . 21 DQ7: Data# Polling........ 21
Figure 4. Data# Polling Algorithm ......... 21
RY/BY#: Ready/Busy# .. DQ6: Toggle Bit I ........... DQ2: Toggle Bit II .......... Reading Toggle Bits DQ6/DQ2 .... DQ5: Exceeded Timing Limits ......
22 22 22 22 23
Erase and Programming Performance . . . . . . . 37 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 37 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 37 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38 TS 040--40-Pin Standard Thin Small Outline Package ......... 38 TSR040--40-Pin Reverse Thin Small Outline Package......... 39 TS 048--48-Pin Standard Thin Small Outline Package ......... 40 TSR048--48-Pin Reverse Thin Small Outline Package......... 41 SO 044--44-Pin Small Outline Package ........ 42 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43 Revision A (May 1997) .. 43 Revision B (January 1998) ..... 43 Revision B+1 (January 1998) ....... 43 Revision B+2 (April 1998)....... 43 Revision C (January 1999) ..... 43 Revision C+1 (March 23, 1999).... 43 Revision C+2 (May 17, 1999) ....... 43 Revision C+3 (July 2, 1999) ......... 43 Revision D (November 16, 1999) .......... 43 Revision E (May 19, 2000) ..... 44 Revision E+1 (December 4, 2000) ........ 44 Revision E+2 (March 23, 2001) .... 44
Am29F016D
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PRODUCT SELECTOR GUIDE
Family Part Number Speed Options (VCC = 5.0 V ± 10%) Max Access Time (ns) CE# Access (ns) OE# Access (ns) -70 70 70 40 -90 90 90 40 Am29F016D -120 120 120 50 -150 150 150 75
Note: See the AC Characteristics section for more information.
BLOCK DIAGRAM
DQ0DQ7 VCC V SS RY/BY# RESET# State Control Command Register Sector Switches Erase Voltage Generator Input/Output Buffers
WE#
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A20
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Am 2 9 F 0 1 6 D
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