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Part: AM29LV001BB-45RFE
Category:
Memory
-> Flash
Description: 1 Megabit ( 128 K X 8-bit ) CMOS 3.0 Volt-only Boot Sector Flash Memory
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29LV001BB-45RFE datasheet File size : 1438 kB
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Datasheet text preview:
PRELIMINARY
Am29LV001B
1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation -- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications -- Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors s Manufactured on 0.35 µm process technology s High performance -- Full voltage range: access times as fast as 55 ns -- Regulated voltage range: access times as fast as 45 ns s Ultra low power consumption (typical values at 5 MHz) -- 200 nA Automatic Sleep mode current -- 200 nA standby mode current -- 7 mA read current -- 15 mA program/erase current s Flexible sector architecture -- One 8 Kbyte, two 4 Kbyte, and seven 16 Kbyte -- Suppor ts full chip erase -- Sector Protection features: Hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporar y Sector Unprotect feature allows code changes in previously locked sectors s Unlock Bypass Mode Program Command -- Reduces overall programming time when issuing multiple program command sequences s Top or bottom boot block configurations available s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 1,000,000 write cycle guarantee per sector s Package option -- 32-pin TSOP -- 32-pin PLCC s Compatibility with JEDEC standards -- Pinout and software compatible with singlepower supply Flash -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion s Erase Suspend/Erase Resume -- Suppor ts reading data from or programming data to a sector that is not being erased s Hardware reset pin (RESET#) -- Hardware method for resetting the device to reading array data
Publication# 21557 Rev: C Amendment/0 Issue Date: April 1998
PRELIMINARY
GENERAL DESCRIPTION
T h e Am29LV001B is a 1 Mbit, 3.0 Volt-only Flash m e m o r y device organized as 131,072 bytes. The Am29LV001B has a boot sector architecture. The device is offered in 32-pin PLCC and 32-pin TSOP packages. The byte-wide (x8) data appears on DQ7 D Q 0 . All read, erase, and program operations are accomplished using only a single power supply. The device can also be programmed in standard EPROM programmers. The standard Am29LV001B offers access times of 45, 55, 70, and 90 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single power supply (2.7 V3.6V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The Am29LV001B is entirely command set compatible w ith the JEDEC sin gle-power-sup ply Flash standard. Commands are written to the command register using standard microprocessor write timings. Regi s t e r contents serve as input to an internal statemachine that controls the erase and programming circuitr y. Write cycles also internally latch addresses and d ata needed for the programming and erase operat i o n s. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase a lg o r i t h m -- a n internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memor y. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When add re sse s have been stable for a specified amount of tim e, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a s e c t o r simultaneously via Fowler-Nordheim tunn e l i n g . The data is programmed using hot electron inject ion.
Am29LV001B
2
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options Regulated Voltage Range: VCC =3.03.6 V Full Voltage Range: VCC = 2.73.6 V Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) 45 45 25 -45R -55 55 55 30 -70 70 70 30 -90 90 90 35 Am29LV001B
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
DQ0DQ7 V CC VSS RESET# Erase Voltage Generator Input/Output Buffers Sector Switches
W E#
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A16
21557C-1
3
Am29LV001B
PRELIMINARY
CONNECTION DIAGRAMS
A11 A9 A8 A13 A14 NC WE# VCC RESET# A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin Standard TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin Reverse TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 A14 NC WE# VCC RESET# A16 A15 A12 A7 A6 A5 A4
RESET#
4 3 2 1 32 31 30 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VSS DQ3 DQ1 DQ2 DQ4 DQ5 DQ6 AmPLLV001 29CC 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE# A10 CE# DQ7
V CC
A12 A15
WE# NC
A16
21557C-2
Am29LV001B
4
PRELIMINARY
PIN CONFIGURATION
A0A16 = 17 addresses DQ0DQ7 = 8 data inputs/outputs C E# OE# WE# RESET# VCC = Chip enable = Output enable = Write enable = Hardware reset pin, active low = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = Device ground = Pin not connected internally
LOGIC SYMBOL
17 A0A16 DQ0DQ7 8
CE# OE# WE# RESET#
V SS NC
21557C-3
5
Am29LV001B
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