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Part: AM29LV002BT-90
Category:
Memory
-> Flash
-> 2 Mb
Description:
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29LV002BT-90 datasheet File size : 1438 kB
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Datasheet text preview:
Am29LV002B
2 Megabit (256 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation -- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications -- Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors s Manufactured on 0.32 µm process technology -- Compatible with 0.5 µm Am29LV002 device s High performance -- Full voltage range: access times as fast as 70 ns -- Regulated voltage range: access times as fast as 55 ns s Ultra low power consumption (typical values at 5 MHz) -- 200 nA Automatic Sleep mode current -- 200 nA standby mode current -- 7 mA read current -- 15 mA program/erase current s Flexible sector architecture -- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and three 64 Kbyte sectors -- Suppor ts full chip erase -- Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors s Unlock Bypass Mode Program Command -- Reduces overall programming time when issuing multiple program command sequences s Top or bottom boot block configurations available s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 1,000,000 write cycle guarantee per sector s 20-year data retention at 125°C -- Reliable operation for the life of the system s Package option -- 40-pin TSOP s Compatibility with JEDEC standards -- Pinout and software compatible with singlepower supply Flash -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion s Ready/Busy# pin (RY/BY#) -- Provides a hardware method of detecting program or erase cycle completion s Erase Suspend/Erase Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset pin (RESET#) -- Hardware method to reset the device to reading array data
This Data Sheet states AMD's current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21520 Rev: D Amendment/+1 Issue Date: November 13, 2000
GENERAL DESCRIPTION
T h e Am29LV002B is an 2 Mbit, 3.0 volt-only Flash me mo ry organized as 262,144 bytes. The device is offered in a 40-pin TSOP package. The byte-wide (x8) data appears on DQ7DQ0. This device requires only a single, 3.0 volt VCC supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device. This device is manufactured using AMD's 0.32 µm process technology, and offers all the features and benefits of the Am29LV002, which was manufactured using 0 . 5 µ m p r o c e s s t e c h n o l o g y. I n a d d i t i o n , t h e A m 2 9 LV 0 0 2 B features unlock bypass programming and in-system sector protection/unprotection. The standard device offers access times of 55, 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention t h e device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. T h e device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Comm a n d s are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that co ntr ol s the erase and programming circuitry. Write cycles also internally latch addresses and data needed fo r the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. D e v i c e erasure occurs by executing the erase c o m m a n d sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatic a l l y preprograms the array (if it is not already p ro gra mme d) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase o p e r a t i o n s in any combination of the sectors of m emor y. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. T h e device offers two power-saving features. When addresses have been stable for a specified amount of tim e, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector s im ul t an e o us ly via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
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Am29LV002B
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29LV002B Device Bus Operations ........ 8
Reading Toggle Bits DQ6/DQ2 ..... 19
Figure 6. Toggle Bit Algorithm ........ 20
DQ5: Exceeded Timing Limits ...... 20 DQ3: Sector Erase Timer ....... 20
Table 6. Write Operation Status..... 21
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 22
Figure 7. Maximum Negative Overshoot Waveform .... 22 Figure 8. Maximum Positive Overshoot Waveform ...... 22
Requirements for Reading Array Data .... 8 Writing Commands/Command Sequences ...... 8 Program and Erase Operation Status ..... 9 Standby Mode ........ 9 Automatic Sleep Mode .... 9 RESET#: Hardware Reset Pin ....... 9 Output Disable Mode ....... 9
Table 2. Am29LV002BT Top Boot Block Sector Address Table..... 10 Table 3. Am29LV002BB Bottom Boot Block Sector Address Table 10
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 22 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ...... 24 Figure 10. Typical ICC1 vs. Frequency .......... 24
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. Test Setup ............ 25 Table 7. Test Specifications .. 25
Key to Switching Waveforms . . . . . . . . . . . . . . . 25
Figure 12. Input Waveforms and Measurement Levels ........ 25
Autoselect Mode ............ 10
Table 4. Am29LV002B Autoselect Codes (High Voltage Method).. 10
Sector Protection/Unprotection ..... 11 Temporary Sector Unprotect ........ 11 Hardware Data Protection ...... 11
Figure 1. Temporary Sector Unprotect Operation ...11
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Operations ........... 26
Figure 13. Read Operations Timings ............ 26
Hardware Reset (RESET#) .... 27
Figure 14. RESET# Timings .......... 27
Low VCC Write Inhibit ..... 11 Write Pulse "Glitch" Protection ..... 11 Logical Inhibit ........ 11 Power-Up Write Inhibit ... 11
Figure 2. In-System Sector Protect/Unprotect Algorithms ......12
Erase/Program Operations ..... 28
Figure 15. Program Operation Timings ......... 29 Figure 16. Chip/Sector Erase Operation Timings .. 30 Figure 17. Data# Polling Timings (During Embedded Algorithms) . 31 Figure 18. Toggle Bit Timings (During Embedded Algorithms) ...... 31 Figure 19. DQ2 vs. DQ6 ........ 32
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 13 Reading Array Data ....... 13 Reset Command ............ 13 Autoselect Command Sequence ........... 13 Byte Program Command Sequence ...... 13 Unlock Bypass Command Sequence .... 14 Chip Erase Command Sequence .......... 14
Figure 3. Program Operation ..........14
Temporary Sector Unprotect ........ 32
Figure 20. Temporary Sector Unprotect Timing Diagram ..... 32 Figure 21. Sector Protect/Unprotect Timing Diagram ........... 33
Alternate CE# Controlled Erase/Program Operations ... 34
Figure 22. Alternate CE# Controlled Write Operation Timings ...... 35
Sector Erase Command Sequence ....... 15 Erase Suspend/Erase Resume Commands ... 15
Figure 4. Erase Operation ......16
Command Definitions .... 17
Table 5. Am29LV002B Command Definitions......... 17
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 18 DQ7: Data# Polling ........ 18
Figure 5. Data# Polling Algorithm .........18
RY/BY#: Ready/Busy# .. 19 DQ6: Toggle Bit I ........... 19 DQ2: Toggle Bit II .......... 19
Erase and Programming Performance . . . . . . . 36 Latchup Characteristics . . . . . . . . . . . . . . . . . . . 36 TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 36 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 37 TS 040--40-Pin Standard TSOP* ......... 37 TSR040--40-Pin Reverse TSOP .......... 38 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 39 Revision A (January 1998) ..... 39 Revision B (June 1998) .......... 39 Revision B+1 (August 1998) ......... 39 Revision C (January 1999) ..... 39 Revision D (November 18, 1999) .......... 39 Revision D+1 (November 13, 2000) ...... 39
Am29LV002B
3
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options Regulated Voltage Range: VCC =3.03.6 V Full Voltage Range: VCC = 2.73.6 V Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) 55 55 30 -55R -70 70 70 30 -90 90 90 35 -120 120 120 50 Am29LV002B
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
RY/BY# VC C V SS RESET# Erase Voltage Generator Input/Output Buffers Sector Switches DQ0DQ7
WE#
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A17
4
Am29LV002B
CONNECTION DIAGRAMS
A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# NC RY/BY# NC A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Standard TSOP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A17 VSS NC NC A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0
A17 VSS NC NC A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 CE# VSS CE# A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Reverse TSOP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# NC RY/BY# NC A7 A6 A5 A4 A3 A2 A1
Am29LV002B
5
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