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Part: AM29LV641DH120RWHEN
Category:
Memory
-> Flash
Description: 64 Megabit ( 4 M X 16-bit ) CMOS 3.0 Volt-only Uniform Sector Flash Memory With Versatilei Control
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29LV641DH120RWHEN datasheet File size : 1450 kB
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Am29LV640D/Am29LV641D
Data Sheet
July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number 22366 Revision B
Amendment +8 Issue Date September 20, 2002
Am29LV640D/Am29LV641D
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO Control
DISTINCTIVE CHARACTERISTICS
s Single power supply operation -- 3.0 to 3.6 volt read, erase, and program operations s VersatileIO control -- Device generates output voltages and tolerates data input voltages on the DQ input/ouputs as determined by the voltage on VIO s High performance -- Access times as fast as 90 ns s Manufactured on 0.23 µm process technology s CFI (Common Flash Interface) compliant -- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices s SecSi (Secured Silicon) Sector region -- 128-word sector for permanent, secure identification through an 8-word random Electronic Serial Number -- May be programmed and locked at the factory or by the customer -- Accessible through a command sequence s Ultra low power consumption (typical values at 3.0 V, 5 MHz) -- 9 mA typical active read current -- 26 mA typical erase/program current -- 200 nA typical standby mode current s Flexible sector architecture -- One hundred twenty-eight 32 Kword sectors s Sector Protection -- A hardware method to lock a sector to prevent program or erase operations within that sector -- Sectors can be locked in-system or via programming equipment -- Temporary Sector Unprotect feature allows code changes in previously locked sectors s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses s Compatibility with JEDEC standards -- Pinout and software compatible with single-power supply Flash -- Superior inadvertent write protection s Minimum 1 million erase cycle guarantee per sector s Package options -- 48-pin TSOP (Am29LV641DH/DL only) -- 56-pin SSOP (Am29LV640DH/DL only) -- 63-ball Fine-Pitch BGA (Am29LV640DU only) -- 64-ball Fortified BGA (Am29LV640DU only) s Erase Suspend/Erase Resume -- Suspends an erase operation to read data from, or program data to, a sect27 -- or that is not being erased, then resumes the erase operation s Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion s Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences s Ready/Busy# pin (RY/BY#) (Am29LV640DU in FBGA package only) -- Provides a hardware method of detecting program or erase cycle completion s Hardware reset pin (RESET#) -- Hardware method to reset the device for reading array data s WP# pin (Am29LV641DH/DL in TSOP, Am29LV640DH/DL in SSOP only) -- At VIL, protects the first or last 32 Kword sector, regardless of sector protect/unprotect status -- At VIH, allows removal of sector protection -- An internal pull up to VCC is provided s ACC pin -- Accelerates programming time for higher throughput during system production s Program and Erase Performance (VHH not applied to the ACC input pin) -- Word program time: 11 µs typical -- Sector erase time: 0.9 s typical for each 32 Kword sector
Publication# 22366 Rev: B Amendment/+8 Issue Date: September 20, 2002
Refer to AMD's Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29LV640DU/Am29LV641DU is a 64 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power supply flash memory devices organized as 4,194,304 words. Data appears o n DQ0-DQ15. The device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 volt VPP is not required for program o r erase operations. The device can also be programmed in standard EPROM programmers. Access times of 90 and 120 ns are available for applications where VIO VCC. Access times of 100 and 120 ns are available for applications where VIO < VCC. The device is offered in 48-pin TSOP, 56-pin SSOP, 63-ball Fine-Pitch BGA and 64-ball Fortified BGA packages. To eliminate bus contention each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. E a ch device requires only a single 3.0 Volt power supply (3.0 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with t h e JEDEC single-power-supply Flash standard. Commands are written to the command register using sta n da rd microprocessor write timing. Register contents serve as inputs to an internal state-machine that c o n tr o l s the erase and programming circuitry. Write c y c l e s also internally latch addresses and data n e e d e d for the programming and erase operations. R e a d in g data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. D e vice erasure occurs by executing the erase command sequence. This initiates the Embedded Erase a l g o ri t h m -- a n internal algorithm that automatically p r e p r o g r a m s the array (if it is not already programmed) before executing the erase operation. Duri n g erase, the device automatically times the erase pulse widths and verifies proper cell margin. The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates and t o le r a t e s on CE# and DQ I/Os to the same voltage l e ve l that is asserted on V I O . V I O is available in two configurations (1.82.9 V and 3.05.0 V) for operation in various system environments. T h e host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, by reading the DQ7 (Data# Polling), or DQ6 (togg le) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. H ar dware data protection measures include a low V C C detector that automatically inhibits write operat io n s during power transitions. The hardware sector p r o te ct io n feature disables both program and erase operations in any combination of sectors of memory. Th is can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to r e ad in g array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The device offers a standby mode as a power-saving fe a ture . Once the system places the device into the standby mode power consumption is greatly reduced. T h e SecSi (Secured Silicon) Sector provides an minimum 128-word area for code or data that can be permanently protected. Once this sector is protected, n o further programming or erasing within the sector can occur. The Write Protect (WP#) feature protects the first or l a st sector by asserting a logic low on the WP# pin. The protected sector will still be protected even during accelerated programming. The accelerated program (ACC) feature allows the system to program the device at a much faster rate. When ACC is pulled high to VHH, the device enters the Unlock Bypass mode, enabling the user to reduce the time needed to do the program operation. This feature is intended to increase factory throughput during system production, but may also be used in the field if desired. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiven e ss. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection.
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Am29LV640D/Am29LV641D
September 20, 2002
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Special Handling Instructions for FBGA/fBGA Packages ......... 8 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11 VersatileIO (VIO) Control ..... 11 Requirements for Reading Array Data .. 11 Writing Commands/Command Sequences .... 12
Table 1. Device Bus Operations .....11
RY/BY#: Ready/Busy# ... 31 DQ6: Toggle Bit I ........... 31
Figure 6. Toggle Bit Algorithm........ 31
DQ2: Toggle Bit II .......... 32 Reading Toggle Bits DQ6/DQ2 ..... 32 DQ5: Exceeded Timing Limits ...... 32 DQ3: Sector Erase Timer ....... 32
Table 11. Write Operation Status ......... 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 7. Maximum Negative Overshoot Waveform ............ 34 Figure 8. Maximum Positive Overshoot Waveform ..... 34
Accelerated Program Operation ......12 Autoselect Functions .....12
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) .......... 36 Figure 10. Typical ICC1 vs. Frequency ........... 36
Standby Mode ...... 12 Automatic Sleep Mode .. 12 RESET#: Hardware Reset Pin ..... 12 Output Disable Mode ..... 13
Table 2. Sector Address Table ........13
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Test Setup........... 37 Table 12. Test Specifications ......... 37
Autoselect Mode ............ 17
Table 3. Autoselect Codes, (High Voltage Method) .....17
Key to Switching Waveforms. . . . . . . . . . . . . . . . 37
Figure 12. Input Waveforms and Measurement Levels.... 37
Sector Group Protection and Unprotection ..... 18
Table 4. Sector Group Protection/Unprotection Address Table .....18
Write Protect (WP#) ....... 19 Temporary Sector Group Unprotect ...... 19
Figure 1. Temporary Sector Group Unprotect Operation ....... 19 Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 20
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38 Read-Only Operations .. 38
Figure 13. Read Operation Timings ..... 38
Hardware Reset (RESET#) .... 39
Figure 14. Reset Timings ...... 39
SecSi (Secured Silicon) Sector Flash Memory Region .......... 21
Table 5. SecSi Sector Contents ......21
Erase and Program Operations .... 40
Figure 15. Program Operation Timings......... Figure 16. Accelerated Program Timing Diagram.. Figure 17. Chip/Sector Erase Operation Timings .. Figure 18. Data# Polling Timings (During Embedded Algorithms)...... Figure 19. Toggle Bit Timings (During Embedded Algorithms)...... Figure 20. DQ2 vs. DQ6........ 41 41 42 43 44 44
Hardware Data Protection ...... 21
Low VCC Write Inhibit ............21 Write Pulse "Glitch" Protection ........22 Logical Inhibit ..........22 Power-Up Write Inhibit ...........22
Common Flash Memory Interface (CFI) . . . . . . . 22
Table 6. CFI Query Identification String ......... 22 System Interface String.......... 23 Table 8. Device Geometry Definition .... 23 Table 9. Primary Vendor-Specific Extended Query ...... 24
Temporary Sector Unprotect ........ 45
Figure 21. Temporary Sector Group Unprotect Timing Diagram ... 45 Figure 22. Sector Group Protect and Unprotect Timing Diagram .. 46
Command Definitions . . . . . . . . . . . . . . . . . . . . . 24 Reading Array Data ....... 24 Reset Command ............ 25 Autoselect Command Sequence ........... 25 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 25 Word Program Command Sequence .... 25
Unlock Bypass Command Sequence ....26 Figure 3. Program Operation .......... 26
Alternate CE# Controlled Erase and Program Operations ..... 47
Figure 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings .... 48
Chip Erase Command Sequence .......... 26 Sector Erase Command Sequence ....... 27 Erase Suspend/Erase Resume Commands ... 27
Figure 4. Erase Operation...... 28
Command Definitions .... 29
Command Definitions.... 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 30 DQ7: Data# Polling ........ 30
Figure 5. Data# Polling Algorithm ......... 30
Erase And Programming Performance . . . . . . . 49 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 49 TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 49 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 50 SSO056--56-Pin Shrink Small Outline Package (SSOP) ...... 50 FBE063--63-Ball Fine-Pitch Ball Grid Array (FBGA) 12 x 11 mm package ....... 51 LAA064--64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm package ....... 52 TS 048--48-Pin Standard TSOP ........... 53 TSR048--48-Pin Reverse TSOP .......... 54 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55
September 20, 2002
Am29LV640D/Am29LV641D
3
PRODUCT SELECTOR GUIDE
Part Number Speed Option Max Access Time (ns) CE# Access Time (ns) OE# Access Time (ns) Note: See "AC Characteristics" for full specifications. VCC = 3.03.6 V, VIO = 3.05.0 V VCC = 3.03.6 V, VIO = 1.82.9 V 90 90 35 90R 101R 100 100 35 Am29LV640D/Am29LV641D 120R 121R 120 120 50
BLOCK DIAGRAM
RY/BY# (Note 1) VCC VSS RESET# Erase Voltage Generator VIO Input/Output Buffers Sector Switches DQ0DQ15
WE# WP# (Note 2) A CC
State Co ntro l Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE # OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A21
Notes: 1. RY/BY# is only available in the FBGA package. 2. WP# is only available in the TSOP and SSOP packages.
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Am29LV640D/Am29LV641D
September 20, 2002
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