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Part: Am42DL1632DB70I
Category:
Memory
-> SRAM
-> 16 Mb
Description: 16 Mbit (2 M X 8-Bit/1 M X 16-Bit) CMOS And 2 Mbit (128 K X 16-Bit) Static RAM
Company: Advanced Micro Devices, Inc.
Datasheet: Download Am42DL1632DB70I datasheet File size : 75 kB
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Datasheet text preview:
Am42DL16x2D
Data Sheet
July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Ple ase contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number 25561 Revision A
Amendment +2 Issue Date February 6, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
Am42DL16x2D
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features
Power supply voltage of 2.7 to 3.3 volt High performance
-- Access time as fast as 70 ns
SOFTWARE FEATURES
Data Management Software (DMS)
-- AMD-supplied software manages data programming and erasing, enabling EEPROM emulation -- Eases sector erase limitations
Package
-- 69-Ball FBGA
Supports Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume
-- Suspends erase operations to allow programming in same bank
Operating Temperature
-- 40°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
-- Data can be continuously read from one bank while executing erase/program functions in other bank -- Zero latency between read and write operations
Data# Polling and Toggle Bits
-- Provides a software method of detecting the status of program or erase cycles
Unlock Bypass Program command
-- Reduces overall programming time when issuing multiple program command sequences
HARDWARE FEATURES
Any combination of sectors can be erased Ready/Busy# output (RY/BY#)
-- Hardware method for detecting program or erase cycle completion
Secured Silicon (SecSi) Sector: Extra 64 KByte sector -- Factor y locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. -- Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed
Hardware reset pin (RESET#)
-- Hardware method of resetting the internal state machine to reading array data
Zero Power Operation
-- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero
WP#/ACC input pin
-- Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status -- Acceleration (ACC) function accelerates program timing
Top or bottom boot block Manufactured on 0.23 µm process technology Compatible with JEDEC standards
-- Pinout and software compatible with single-power-supply flash standard
Sector protection
-- Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector -- Temporar y Sector Unprotect allows changing data in protected sectors in-system
PERFORMANCE CHARACTERISTICS
High performance
-- 70 ns access time -- Program time: 4 µs/word typical utilizing Accelerate function
SRAM Features
Power dissipation
-- Operating: 20 mA maximum -- Standby: 10 µA maximum
Ultra low power consumption (typical values)
-- 2 mA active read current at 1 MHz -- 10 mA active read current at 5 MHz -- 200 nA in standby or automatic sleep mode
Minimum 1 million write cycles guaranteed per sector 20 Year data retention at 125°C
-- Reliable operation for the life of the system
CE1#s and CE2s Chip Select Power down features using CE1#s and CE2s Data retention supply voltage: 1.5 to 3.3 volt Byte data control: LB#s (DQ0DQ7), UB#s (DQ8DQ15)
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 25561 Rev: A Amendment/+2 Issue Date: February 6, 2004
Refer to AMD's Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION Am29DL16xD Features
The Am29DL16xD family is a 16 megabit, 3.0 volt-only flash memory device, organized as 1,048,576 words of 16 bits or 2,097,152 bytes of 8 bits each. Word mode d a t a appears on DQ15DQ0; byte mode data app e a r s on DQ7DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC s u p p l y, and c a n also be programmed in standard EPROM programmers. The device is available with access times of 70 ns or 85 ns. The device is offered in a 69-ball FBGA package. Standard control pins--chip enable (CE#f), write enable (WE#), and output enable (OE#)--control norm a l read and wr i t e operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supp l y for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs t o state which piece of data is to be updated, and where the updated data is located in the system. This i s a n ad v a n t a g e c o m p a r e d t o s y s t e m s wh e r e user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory devic es), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD prov i d e s this software to simplify system design and software integration efforts. The device offers complete compatibility with the JE DEC single-power-supply Flash command set s t a n d a rd . Commands are written to the command register using standard microprocessor write timings. Re ad in g data out of the device is similar to reading from other Flash or EPROM devices. T h e host system can detect whether a program or erase operation is complete by using the device stat u s bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V C C detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memo r y. T h i s c a n b e a c h i e v e d i n - s y s t e m o r v i a programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. T h e system can also place the device into the s t a n d by mode. Power consumption is greatly reduced in both modes.
Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture provides s i mu l t a n e o u s operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to prog r a m or erase in one bank, then immediately and simultaneously read from the other bank, with zero latenc y. This releases the system from waiting for the completion of program or erase operations. The Am29DL16xD devices uses multiple bank architectures to provide flexibility for different applications. Fo u r devices are available with the following bank sizes:
Device DL161 DL162 DL163 DL164 Bank 1 0.5 Mb 2 Mb 4 Mb 8 Mb Bank 2 15.5 Mb 14 Mb 12 Mb 8 Mb
The Secured Silicon (SecSi) Sector is an extra 64 Kb it sector capable of being permanently locked by AMD or customers. The SecSi Sector Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Fa c t o r y locked parts provide several options. The S e c S i Sector may store a secure, random 16 byte ESN (Electronic Serial Number). Customer Lockable pa r ts may utilize the SecSi Sector as bonus space,
2
Am42DL16x2D
February 6, 2004
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Handling Instructions for FBGA Package ........... 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations--Flash Word Mode (CIOf = VIH), SRAM Word Mode (CIOs = VCC) ....11 Table 2. Device Bus Operations--Flash Byte Mode (CIOf = VSS), SRAM Word Mode (CIOs = VCC) ....12
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 25 Byte/Word Program Command Sequence ..... 25 Unlock Bypass Command Sequence .......... 25
Figure 3. Program Operation ......... 26
Chip Erase Command Sequence .......... 26 Sector Erase Command Sequence ....... 26 Erase Suspend/Erase Resume Commands ... 27
Figure 4. Erase Operation..... 27 Table 14. Command Definitions...... 28 Table 15. Autoselect Device ID Codes ......... 28
Write Operation Status . . . . . . . . . . . . . . . . . . . . 29 DQ7: Data# Polling ........ 29
Figure 5. Data# Polling Algorithm ........ 29
Word/Byte Configuration ....... 13 Requirements for Reading Array Data .. 13 Writing Commands/Command Sequences .... 13 Accelerated Program Operation ......... 13 Autoselect Functions .. 13 Simultaneous Read/Write Operations with Zero Latency ....... 13 Standby Mode ...... 14 Automatic Sleep Mode .. 14 RESET#: Hardware Reset Pin ..... 14 Output Disable Mode ..... 14
Table 3. Device Bank Division ........14 Table 4. Sector Addresses for Top Boot Sector Devices ...... 15 Table 5. SecSi Sector Addresses for Top Boot Devices .......15 Table 6. Sector Addresses for Bottom Boot Sector Devices ..16 Table 7. SecSiTM Addresses for Bottom Boot Devices .........16
RY/BY#: Ready/Busy# ... 30 DQ6: Toggle Bit I ........... 30
Figure 6. Toggle Bit Algorithm........ 30
DQ2: Toggle Bit II .......... 31 Reading Toggle Bits DQ6/DQ2 ..... 31 DQ5: Exceeded Timing Limits ...... 31 DQ3: Sector Erase Timer ....... 31
Table 16. Write Operation Status ......... 32
Autoselect Mode ............ 17 Sector/Sector Block Protection and Unprotection ......... 17
Table 8. Top Boot Sector/Sector Block Addresses for Protection/Unprotection .......17 Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection ....17
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 33 Industrial (I) Devices ... 33 VCCf/VCCs Supply Voltage ......... 33 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34 CMOS Compatible ......... 34 SRAM DC and Operating Characteristics . . . . . 35 Zero-Power Flash ........ 36
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ....... 36 Figure 10. Typical ICC1 vs. Frequency ........... 36
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Test Setup........... 37 Table 17. Test Specifications ......... 37
Write Protect (WP#) ....... 18 Temporary Sector/Sector Block Unprotect ..... 18
Figure 1. Temporary Sector Unprotect Operation... 18 Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms .... 19
Key To Switching Waveforms . . . . . . . . . . . . . . . 37
Figure 12. Input Waveforms and Measurement Levels ........ 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38 SRAM CE#s Timing ....... 38
Figure 13. Timing Diagram for Alternating Between SRAM to Flash ....... 38
SecSi (Secured Silicon) Sector Flash Memory Region .......... 20 Factory Locked: SecSi Sector Programmed and Protected At the Factory ........ 20 Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory .. 20 Hardware Data Protection ...... 20 Low VCC Write Inhibit .. 20 Write Pulse "Glitch" Protection ........... 21 Logical Inhibit .... 21 Power-Up Write Inhibit ......... 21 Common Flash Memory Interface (CFI) . . . . . . . 21
Table 10. CFI Query Identification String ....... System Interface String.......... Table 12. Device Geometry Definition ........... Table 13. Primary Vendor-Specific Extended Query .... 21 22 22 23
Flash Read-Only Operations ....... 39
Figure 14. Read Operation Timings ..... 39
Hardware Reset (RESET#) .... 40
Figure 15. Reset Timings ...... 40
Flash Word/Byte Configuration (CIOf) ... 41
Figure 16. CIOf Timings for Read Operations........ 41 Figure 17. CIOf Timings for Write Operations........ 41
Flash Erase and Program Operations ... 42
Figure 18. Program Operation Timings......... Figure 19. Accelerated Program Timing Diagram.. Figure 20. Chip/Sector Erase Operation Timings .. Figure 21. Back-to-back Read/Write Cycle Timings .... Figure 22. Data# Polling Timings (During Embedded Algorithms). Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... Figure 24. DQ2 vs. DQ6........ 43 43 44 45 45 46 46
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 24 Reading Array Data ....... 24 Reset Command ............ 24 Autoselect Command Sequence ........... 24
Temporary Sector/Sector Block Unprotect ..... 47
Figure 25. Temporary Sector/Sector Block Unprotect Timing Diagram...... 47
February 6, 2004
Am42DL16x2D
3
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